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參數(shù)資料
| 型號(hào)： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁(yè)數(shù)： | 18/124頁(yè) |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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82559 — Networking Silicon
8
Datasheet
3.2.2
Interface Control Signals
Symbol
Type
Name and Function
FRAME#
S/T/S
Cycle Frame.
The cycle frame signal is driven by the current master
to indicate the beginning and duration of a transaction. FRAME# is
asserted to indicate the start of a transaction and de-asserted during
the final data phase.
IRDY#
S/T/S
Initiator Ready.
The initiator ready signal indicates the bus master’s
ability to complete the current data phase and is used in conjunction
with the target ready (TRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
TRDY#
S/T/S
Target Ready.
The target ready signal indicates the selected device’s
ability to complete the current data phase and is used in conjunction
with the initiator ready (IRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
STOP#
S/T/S
Stop.
The stop signal is driven by the target to indicate to the initiator
that it wishes to stop the current transaction. As a bus slave, STOP# is
driven by the 82559 to inform the bus master to stop the current
transaction. As a bus master, STOP# is received by the 82559 to stop
the current transaction.
IDSEL
IN
Initialization Device Select.
The initialization device select signal is
used by the 82559 as a chip select during PCI configuration read and
write transactions. This signal is provided by the host in PCI systems.
In a CardBus system, this pin should not be connected.
DEVSEL#
S/T/S
Device Select.
The device select signal is asserted by the target once
it has detected its address. As a bus master, the DEVSEL# is an input
signal to the 82559 indicating whether any device on the bus has been
selected. As a bus slave, the 82559 asserts DEVSEL# to indicate that
it has decoded its address as the target of the current transaction.
REQ#
T/S
Request.
The request signal indicates to the bus arbiter that the
82559 desires use of the bus. This is a point-to-point signal and every
bus master has its own REQ#.
GNT#
IN
Grant.
The grant signal is asserted by the bus arbiter and indicates to
the 82559 that access to the bus has been granted. This is a point-to-
point signal and every master has its own GNT#.
INTA#
O/D
Interrupt A.
The interrupt A signal is used to request an interrupt by
the 82559. This is an active low, level triggered interrupt signal.
SERR#
O/D
System Error.
The system error signal is used to report address
parity errors. When an error is detected, SERR# is driven low for a
single PCI clock.
PERR#
S/T/S
Parity Error.
The parity error signal is used to report data parity errors
during all PCI transactions except a Special Cycle. The parity error pin
is asserted two clock cycles after the error was detected by the device
receiving data. The minimum duration of PERR# is one clock for each
data phase where an error is detected. A device cannot report a parity
error until it has claimed the access by asserting DEVSEL# and
completed a data phase.
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