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參數(shù)資料
| 型號(hào)： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁(yè)數(shù)： | 35/124頁(yè) |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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Networking Silicon — 82559
Datasheet
25
When the 82559 is almost out of resources on the transmit DMA (that is, the transmit FIFO is
almost full), it attempts to terminate the read transaction on the nearest cache line boundary
when possible.
When the arbitration counter’s feature is enabled (in other words, the Transmit DMA
Maximum Byte Count value is set in the Configure command), the 82559 switches to other
pending DMAs on cache line boundary only.
Note the following:
This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance.
This feature should be used only when the CLS register in PCI Configuration space is set to 8
or 16.
The 82559 reads all control data structures (including Receive Buffer Descriptors) from the
first Dword (even if it is not required) in order to maintain cache line alignment.
4.2.1.2.3
Error Handling
Data Parity Errors:
As an initiator, the 82559 checks and detects data parity errors that occur
during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register,
bit 6), the 82559 also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration
Status register, bit 8). In addition, if the error was detected by the 82559 during read cycles, it sets
the Detected Parity Error bit (PCI Configuration Status register, bit 15).
4.2.2
PCI Mode Pin
During PCI reset the 82559 samples the PCIMODE# (multiplexed with FLA0) input signal to
determine the nature of the host system. If the PCIMODE# signal is sampled low when RST# is
active, the host system bus is a PCI system. If PCIMODE# is sampled high during reset, the host
system is a CardBus system. In a CardBus system, the PCIMODE# pin should be connected to a
pull-up resistor; otherwise, the 82559 assumes it is a PCI system.
4.2.3
Clockrun Signal
The CLKRUN# signal is used to control the PCI clock as defined in the CardBus specification and
PCI Mobile design guide and is compliant with both the CardBus specification and PCI Mobile
design guide. This signal is active in both the CardBus and PCI bus operating modes. The Clockrun
signal is an open drain I/O signal. It is used as a bidirectional channel between the host and the
devices.
The host de-asserts the CLKRUN# signal to indicate that the clock is about to be stopped or
slowed down to a non-operational frequency.
The host asserts the CLKRUN# signal when the interface clock is either running at a normal
operating frequency or about to be started.
The 82559 asserts the CLKRUN# signal to indicate that it needs the PCI clock to prevent the
host from stopping the PCI clock or to request that the host restore the clock if it was
previously stopped.
Proper operation requires that the system latency from the nominal PCI CLK to CLKRUN#
assertion should be less than 0.5
μ
s. If the system latency is longer than 0.5
μ
s, the occurrence of
receive overruns increases. For use in these types of systems, the Clockrun functionality should be
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