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參數(shù)資料
| 型號： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁數(shù)： | 103/124頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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Networking Silicon — 82559
Datasheet
93
11.0
82559 Test Port Functionality
11.1
Introduction
The 82559’s NAND Tree Test Access Port (TAP) is the access point for test data to and from the
device. The port provides the ability to perform basic production level testing. The port provides
two functions:
The synchronous IC validation mode is used in the production of the device. This mode gives
the signals their names (for example, Testability Port Clock [TCK]).
The 82559 also supports asynchronous testing modes. These test modes support the validation
of connections at the board level.
11.2
Asynchronous Test Mode
Four asynchronous test modes are supported for system level design use. The modes are selected
through the use of the test port input pin in static combinations. The test port pins are Test Port
(TEST), Test Port Data Input (TI), Test Port Execute Enable (TEXEC) and Test Port Clock (TCK).
During normal operation the TEST pin must be pulled down through a resistor (pulling TEST high
enables the test mode). All other port inputs may have a pull-down at the designers discretion.
11.3
Test Function Description
The 82559 TAP mode supports several tests that can be used in board level design. These tests help
verify basic functionality as well as test the integrity of solder connection on the board. The tests
are described in the following subsections.
11.3.1
Tristate
The tristate command sets all 82559 input and output pins into a tristate (high-Z) mode (all internal
pull-ups and pull-downs are disabled). This mode is entered by setting the following test pin
combination and resetting the device:
TEST = 1
TEXEC = 0
TCK = 0
TI = 1
11.3.2
NAND Tree
The NAND Tree test mode is the most useful of the asynchronous test modes. It enables the
placement of the 82559 to be validated at board test. The NAND Tree was chosen for its speed
advantages. Modern automated test equipment can perform a complete peripheral scan without
support at the board level. This command connects all outputs of the input buffers in the device
periphery into a NAND Tree scheme. All the output drivers of the output buffers, except the Test
Port Data Output (TO) pin, are put into high-Z mode. These pins are driven to affect the output of
the tree. There are two separate chains and associated outputs for speed. Any hard strapped pins
will prevent the tester from scanning correctly. This mode is entered by placing the test pins in the
following combination:
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