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參數(shù)資料
| 型號： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁數(shù)： | 13/124頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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Networking Silicon — 82559
Datasheet
3
2.0
82559 Architectural Overview
Figure 1
is a high level block diagram of the 82559. It is divided into five main subsystems: a
parallel subsystem, a FIFO subsystem, the Total Cost of Ownership (TCO) subsystem, the 10/100
Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and the 10/100 Mbps
physical layer (PHY) unit.
2.1
Parallel Subsystem Overview
The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem,
passing data (such as transmit, receive, and configuration data) and command and status
parameters between these two blocks.
The dual function LAN and modem interface provides a complete glueless connection to the PCI
bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82559 provides 32 bits of
addressing and data, as well as the complete control interface to operate on a PCI bus. As a PCI
target, it follows the PCI configuration format which allows all accesses to the 82559 to be
automatically mapped into free memory and I/O space upon initialization of a PCI system. For
processing of transmit and receive frames, the 82559 operates as a master on the PCI bus, initiating
zero wait state transfers for accessing these data parameters.
The 82559 Control/Status Register Block is part of the PCI target element. The Control/Status
Register block consists of the following 82559 internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPROM Control, Modem Control and Management Data Interface
(MDI) Control.
The micromachine is an embedded processing unit contained in the 82559 that enables Adaptive
Technology. The micromachine accesses the 82559 microcode ROM working its way through the
operation codes, opcodes (or instructions), contained in the ROM to perform its functions.
Parameters accessed from memory such as pointers to data buffers are also used by the
Figure 1. 82559 Block Diagram
10/100 Mbps
CSMA/CD
Data Interface Unit
(DIU)
100BASE-TX/
10BASE-T
PHY
Four Channel
Addressing Unit -
DMA
PCI Bus
Interface Unit
(BIU)
PCI Target and
Flash/Modem/EEPROM
Interface
Micro-
machine
Dual
Ported
FIFO
3 Kbyte
Rx FIFO
FIFO Control
3 Kbyte
Tx FIFO
SMB
Interface
Local Memory/
Modem Interface
SMB
Interface
PCI/
CardBus
Interface
TPE
Interface
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