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參數(shù)資料
| 型號(hào)： | 82559 |
| 廠(chǎng)商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線(xiàn)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁(yè)數(shù)： | 69/124頁(yè) |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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Networking Silicon — 82559
Datasheet
59
Note:
Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b
only if the value of 00010000b (16H) is written to this register. All other bits are read only and will
return a value of 0b on read.
This register is expected to be written by the BIOS and the 82559 driver should not write to it.
8.1.7
PCI Latency Timer
The Latency Timer register is a byte wide register. When the 82559 is acting as a bus master, this
register defines the amount of time, in PCI clock cycles, that it may own the bus.
8.1.8
PCI Header Type
The Header Type register is a byte read only register. It is equal to 00H for a single function
Ethernet card and 80H for a combination Ethernet and modem card. The value of the header type is
set by the EEPROM (
Section 4.7, “Serial EEPROM Interface” on page 33
). In a dual function card,
the OS will read the next configuration registers bank at offset 100H.
8.1.9
PCI Base Address Registers
One of the most important functions for enabling superior configurability and ease of use is the
ability to relocate PCI devices in address spaces. The 82559 contains three types of Base Address
Registers (BARs). Two are used for memory mapped resources, and one is used for I/O mapping.
Each register is 32 bits wide. The least significant bit in the BAR determines whether it represents
a memory or I/O space. The figures below show the layout of a BAR for both memory and I/O
mapping. After determining this information, power-up software can map the memory and I/O
controllers into available locations and proceed with system boot. In order to do this mapping in a
device independent manner, the base registers for this mapping are placed in the predefined header
portion of configuration space. Device drivers can then access this configuration space to determine
the mapping of a particular device.
Figure 25. Base Address Register for Memory Mapping
Base Address
0
0
31
4 3 2 1
Prefetchable
The prefetchable bit is set to ‘0’ in 82559 devices
Type
00 - locate anywhere in 32-bit address space
01 - locate below 1 Mbyte
10 - locate anywhere in 64-bit address space
11 - reserved
Memory space indicator
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