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參數(shù)資料
| 型號(hào)： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁數(shù)： | 33/124頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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Networking Silicon — 82559
Datasheet
23
Read Accesses:
The 82559 performs block transfers from host system memory in order to perform
frame transmission on the serial link. In this case, the 82559 initiates zero wait state
memory read
burst cycles for these accesses. The length of a burst is bounded by the system and the 82559’s
internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA
Maximum Byte Count in the Configure command. The Transmit DMA Maximum Byte Count
value indicates the maximum number of transmit DMA PCI cycles that will be completed after an
82559 internal arbitration. (Details on the Configure command are described in the
10/100 Mbit
Family Software Developer’s Manual
.)
The 82559, as the initiator, drives the address lines AD[31:0], the command and byte enable lines
C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559 asserts IRDY# to support zero
wait state burst cycles. The target signals the 82559 that valid data is ready to be read by asserting
the TRDY# signal.
Write Accesses:
The 82559 performs block transfers to host system memory during frame
reception. In this case, the 82559 initiates memory write burst cycles to deposit the data, usually
without wait states. The length of a burst is bounded by the system and the 82559’s internal FIFO
threshold. The length of a write burst may also be bounded by the value of the Receive DMA
Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value
indicates the maximum number of receive DMA PCI transfers that will be completed before the
82559 internal arbitration. (Details on the Configure command are described in the
10/100Mbit
Family Software Developer’s Manual
.)
The 82559, as the initiator, drives the address lines AD[31:0], the command and byte enable lines
C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559 asserts IRDY# to support zero
wait state burst cycles. The 82559 also drives valid data on AD[31:0] lines during each data phase
(from the first clock and on). The target controls the length and signals completion of a data phase
by de-assertion and assertion of TRDY#.
Cycle Completion:
The 82559 completes (terminates) its initiated memory burst cycles in the
following cases:
Normal Completion
: All transaction data has been transferred to or from the target device (for
example, host main memory).
Backoff
: Latency Timer has expired and the bus grant signal (GNT#) was removed from the
82559 by the arbiter, indicating that the 82559 has been preempted by another bus master.
Transmit or Receive DMA Maximum Byte Count
: The 82559 burst has reached the length
specified in the Transmit or Receive DMA Maximum Byte Count field in the Configure
command block. (Details relating to this field and the Configure command are described in the
10/100 Mbit Family Software Developer’s Manual
.)
Target Termination
: The target may request to terminate the transaction with a target-
disconnect, target-retry, or target-abort. In the first two cases, the 82559 initiates the cycle
again. In the case of a target-abort, the 82559 sets the Received Target-Abort bit in the PCI
Configuration Status field (PCI Configuration Status register, bit 12) and does not re-initiate
the cycle.
Master Abort
: The target of the transaction has not responded to the address initiated by the
82559 (in other words, DEVSEL# has not been asserted). The 82559 simply de-asserts
FRAME# and IRDY# as in the case of normal completion.
Error Condition
: In the event of parity or any other system error detection, the 82559
completes its current initiated transaction. Any further action taken by the 82559 depends on
the type of error and other conditions.
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