參數(shù)資料
型號: 82559
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器)
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196
封裝: 15 X 15 MM, BGA-196
文件頁數(shù): 27/124頁
文件大小: 1332K
代理商: 82559
Networking Silicon — 82559
Datasheet
17
CPU accesses to the EEPROM through its CSR
CPU accesses to the 82559 PORT address via the CSR
CPU accesses to the MDI control register in the CSR
CPU accesses to the Flash control register in the CSR
CPU accesses to the 128 Kbyte Flash
The CSR and the 1 Mbyte Flash buffer are considered by the 82559 as two totally separated
memory spaces. The 82559 provides separate Base Address Registers (BARs) in the configuration
space to distinguish between them. The size of the CSR memory space is 4 Kbyte in the memory
space and 64 bytes in the I/O space. The 82559 treats accesses to these memory spaces differently.
4.2.1.1.1
Control/Status Register (CSR) Accesses
The 82559 supports zero wait state
single cycle memory or I/O mapped accesses to its CSR space.
Separate BARs request 4 Kbytes of memory space and 64 bytes of I/O space to accomplish this.
Based on its needs, the software driver will use either memory or I/O mapping to access these
registers. The 82559 provides 4 valid Kbytes of CSR space, which include the following elements:
System Control Block (SCB) registers
PORT register
Flash control register
EEPROM control register
MDI control register
Flow control registers
CardBus registers
The figures below show CSR zero wait state I/O read and write cycles. In the case of accessing the
Control/Status Registers, the CPU is the initiator and the 82559 is the target of the transaction.
Figure 2. Control/Status Register I/O Read Cycle
S
8
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3
4
2
1
5
6
7
8
9
ADDR
DATA
I/O RD
BE#
STOP#
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