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參數(shù)資料
| 型號(hào)： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁(yè)數(shù)： | 52/124頁(yè) |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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82559 — Networking Silicon
42
Datasheet
The magnetics module that is external to the PHY unit converts I
TDP
and I
TDN
to the 2.0 V
pp
, as
required by the TP-PMD specification. The same magnetics used for 100BASE-TX mode should
also work in 10BASE-T mode. The following is a list of current magnetics modules available from
several vendors:
5.1.3
100BASE-TX Receive Blocks
The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive
differential pair. Due to the advanced digital signal processing design techniques employed, the
PHY unit will accurately receive valid data from Category-5 (CAT5) UTP and Type 1 STP cable of
length well in excess of 100 meters.
5.1.3.1
Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the shape of the received signal, equalizing the signal to meet
superior Data Dependent Jitter performance.
5.1.3.2
Receive Clock and Data Recovery
The clock recovery circuit uses advanced digital signal processing technology to compensate for
various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data
to the MLT-3 decoder.
5.1.3.3
MLT-3 Decoder, Descrambler, and Receive Digital Section
The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B
symbols originated in the transmitter. The descrambling is based on synchronization to the transmit
11-bit Linear Feedback Shift Register (LFSR) during idle. The data is decoded at the 4B/5B
decoder. Once the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA
unit.
5.1.3.4
100BASE-TX Receive Framing
The PHY unit does not differentiate between the fields of the MAC frame containing preamble,
start of frame delimiter, data and CRC. During 100 Mbps reception, the PHY unit differentiates
between the idle condition ("L" symbols on the wire) and the preamble or start of frame delimiter.
When two non-consecutive bits are 0b within 10 bits (125 Mbps 5B data coding) the PHY unit
immediately asserts carrier sense. When the “JK” symbols (“11000, 10001”) are fully recognized,
the PHY unit provides the received data to the CSMA unit. If the “JK” symbol is not recognized
(“false carrier sense”), the carrier sense is immediately de-asserted and a receive error is indicated.
Table 3. Magnetics Modules
Vendor
Model/Type
100BASE-TX
10BASE-T
Delta
LF8200A
Yes
Yes
Pulse Engineering
PE-68515
Yes
Yes
Pulse Engineering
H1012
Yes
Yes
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