
62
Software Environment
Chapter 3
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
Figure 53. Gate Descriptor
3.6
Exceptions and Interrupts
Table 11 summarizes the exceptions and interrupts.
DPL
0
Type
Offset 31–16
P
Segment Selector
Offset 15–0
9
8
7
6
5
4
3
2
1
0
10
11
12
13
14
15
16
17
18
19
20
21
31 30 29 28 27 26 25 24 23 22
Reserved
Symbol
P
DPL
DT
Type
Description
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
See Table 10 on page 61
Bits
15
14-13
12
11-8
Table 11. Summary of Exceptions and Interrupts
Interrupt
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
0–255
Interrupt Type
Cause
Divide by Zero Error
Debug
Non-Maskable Interrupt
Breakpoint
Overflow
Bounds Check
Invalid Opcode
Device Not Available
Double Fault
Reserved - Interrupt 13
Invalid TSS
Segment Not Present
Stack Segment
General Protection
Page Fault
Floating-Point Error
Alignment Check
Software Interrupt
DIV, IDIV
Debug trap or fault
NMI signal sampled asserted
Int 3
INTO
BOUND
Invalid instruction
ESC and WAIT
Fault occurs while handling a fault
—
Task switch to an invalid segment
Instruction loads a segment and present bit is 0 (invalid segment)
Stack operation causes limit violation or present bit is 0
Segment related or miscellaneous invalid actions
Page protection violation or a reference to missing page
Arithmetic error generated by floating-point instruction
Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are set to 1.)
INT n