
90
Software Environment
Chapter 3
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
PFRSQIT1 mmreg, mem64
PFRSQRT mmreg1, mmreg2
PFRSQRT mmreg, mem64
PFSUB mmreg1, mmreg2
PFSUB mmreg, mem64
PFSUBR mmreg1, mmreg2
PFSUBR mmreg, mem64
PI2FD mmreg1, mmreg2
PI2FD mmreg, mem64
PMULHRW mmreg1, mmreg2
PMULHRW mmreg1, mem64
PREFETCH mem8
1
PREFETCHW mem8
1,2
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
A7h
97h
97h
9Ah
9Ah
AAh
AAh
0Dh
0Dh
B7h
B7h
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
short
short
short
short
short
short
short
short
short
short
short
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
0Fh
0Dh
mm-000-xxx
vector
load
0Fh
0Dh
mm-001-xxx
vector
load
Notes:
1.
2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2E+ processor, this instruction performs in the same man-
ner as the PREFETCH instruction.
For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched.
Table 16.
3DNow! Technology DSP Extensions
Instruction Mnemonic
Prefix
Byte(s)
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
Opcode
Byte
1Ch
1Ch
8Ah
8Ah
8Eh
8Eh
0Ch
0Ch
BBh
BBh
ModR/M
Byte
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
Decode
Type
short
short
short
short
short
short
short
short
short
short
RISC86
Operations
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
PF2IW mmreg1, mmreg2
PF2IW mmreg, mem64
PFNACC mmreg1, mmreg2
PFNACC mmreg, mem64
PFPNACC mmreg1, mmreg2
PFPNACC mmreg, mem64
PI2FW mmreg1, mmreg2
PI2FW mmreg, mem64
PSWAPD mmreg1, mmreg2
PSWAPD mmreg, mem64
Table 15. 3DNow! Instructions (continued)
Instruction Mnemonic
Prefix
Byte(s)
Opcode
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations