
14
Internal Architecture
Chapter 2
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
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Long decodes—x86 instructions less than or equal to 11
bytes in length
Vector decodes—complex x86 instructions
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Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the executions units.
Scheduler/Instruction
Control Unit
The centralized scheduler or buffer is managed by the
Instruction Control Unit (ICU). The ICU buffers and manages
up to 24 RISC86 operations at a time. This equals from 6 to 12
x86 instructions. This buffer size (24) is perfectly matched to
the processor’s six-stage RISC86 pipeline and four
RISC86-operations decode rate.
The scheduler accepts as many as four RISC86 operations at a
time from the decoders and retires up to four RISC86
operations per clock cycle. The ICU is capable of
simultaneously issuing up to six RISC86 operations at a time to
the execution units. This consists of the following types of
operations:
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Memory load operation
Memory store operation
Complex integer, MMX or 3DNow! register operation
Simple integer, MMX or 3DNow! register operation
Floating-point register operation
Branch condition evaluation
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Registers
When managing the RISC86 operations, the ICU uses 69
physical registers contained within the RISC86
microarchitecture.
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Forty-eight of the physical registers are located in a general
register file.
Twenty-four of these are rename registers.
The other twenty-four are committed or architectural
registers, consisting of 16 scratch registers and 8 registers
that correspond to the x86 general-purpose registers—
EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI.