
Chapter 9
Cache Organization
221
23542A/0—September 2000
AMD-K6-2E+ Embedded Processor Data Sheet
Preliminary Information
9.10
Cache States
Table 39 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines.
Table 39. L1 and L2 Cache States for Read and Write Accesses
Type
Cache State Before Access
1
Access Type
Cache State After Access
MESI State
2
L1
I
I
E
S
M
I
I
I
I
I
I
L2
I
I
–
–
–
E
S
M
M
I
I
L1
I
L2
I
Cache
Read
Read Miss L1,
Read Miss L2
Single read from bus
Burst read from bus, fill L1 and L2
3
–
–
–
Fill L1
Fill L1
Fill L1
Fill L1
Single write to bus
6
Burst read from bus, fill L1 and L2, write to L1
7
Burst read from bus, fill L1 and L2, write to
L1 and L2, single write to bus
7
Write to L1,
single write to bus
Write to L1 and L2,
single write to bus
Write to L1
Write to L2
6
Write to L2, single write to bus
6
Write to L2
6
Fill L1, write to L1
7
Write to L2, single write to bus
7
Fill L1, write to L1
7
S or E
4
E
S
M
E
S
M
E
5
I
M
8
S or E
4
–
–
–
E
S
E
M
5
I
E
8
Read Hit L1
Read Miss L1,
Read Hit L2
Cache
Write
Write Miss L1
Write Miss L2
I
I
S
9
S
9
Write Hit L1
S
I
S or E
4
I
S
S
S or E
4
S or E
4
E or M
I
I
I
I
I
I
–
E
S
M
E
S
M
M
I
I
I
M
–
M
Write Miss L1
Write Hit L2
S or E
4
M
E
S or E
4
E
S or E
4
M
Notes:
1.
M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and
are treated as “valid” states.
2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.
3. If CACHE# is driven Low and KEN# is sampled asserted.
4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or
WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.