
Chapter 5
Signal Descriptions
111
23542A/0—September 2000
AMD-K6-2E+ Embedded Processor Data Sheet
Preliminary Information
5.22
FERR# (Floating-Point Error)
Pin Attribute
Output
Summary
The assertion of FERR# indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-
compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 237 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR# signal.
The processor is designed so that FERR# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
The processor asserts FERR# on the instruction boundary of
the next floating-point instruction, MMX instruction, 3DNow!
instruction, or WAIT instruction that occurs following the
floating-point instruction that caused the unmasked
floating-point exception—that is, FERR# is not asserted at the
time the exception occurs. The IGNNE# signal does not affect
the assertion of FERR#.
FERR# is negated during the following conditions:
I
Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
Under certain circumstances, following the successful
execution of the floating-point instructions FLDCW,
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
Following the falling transition of RESET
I
I
FERR# is always driven except in the Three-State Test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 116 for
more details on floating-point exceptions.