
54
Software Environment
Chapter 3
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
3.3
Memory Management Registers
The AMD-K6-2E+ processor controls segmented memory
management with the registers listed in Table 8. Figure 44
shows the formats of these registers.
Figure 44. Memory Management Registers
Table 8.
Memory Management Registers
Register Name
Global Descriptor Table Register
Interrupt Descriptor Table Register
Local Descriptor Table Register
Task Register
Function
Contains a pointer to the base of the global descriptor table
Contains a pointer to the base of the interrupt descriptor table
Contains a pointer to the local descriptor table of the current task
Contains a pointer to the task state segment of the current task
15
0
16-Bit Limit
16
47
32-Bit Linear Base Address
Global and Interrupt Descriptor Table Registers
31
0
63
32-Bit Limit
32
32-Bit Linear Base Address
15
0
Local Descriptor Table Register and Task Register
Attributes
15
0
Selector