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XRT79L71
PRELIMINARY
549
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
2.
As mentioned earlier, the Receive SSM Controller block will generate this particular interrupt whenever it cannot
identify the "SSM Multi-Frame" pattern (within Bits 6 and 7 of the MA byte) within the incoming E3 frame. If the
Receive SSM Controller block is generating this interrupt, then either of the following phenomenon is occurring
a. The user has (in programmable logic) incorrectly implemented the generation of the "SSM Multi-Frame" pattern
within the "Transmitting" Terminal (which the Receive SSM Controller block circuitry does not recognize), or
b. The Receive Section of the XRT79L71 is currently receiving an erred E3 signal. In this case, the user is advised to
check and verify that the Receive E3 Framer block is NOT declaring the LOS or LOF/OOF defect condition. Further,
the user should verify that the Receive E3 Framer block is not flagging EM Byte or Framing Alignment byte errors as
well.
6.3.5
RECEIVE LAPD CONTROLLER BLOCK
The Receive LAPD Controller block is the fifth functional block within the Receive Direction of the XRT79L71
that we will discuss for E3, ITU-T G.832 Clear-Channel Framer Applications.
illustration of the Receive Direction circuitry whenever the XRT79L71 has been configured to operate in the E3,
ITU-T G.832 Clear-Channel Framer Mode, with the Receive LAPD Controller block highlighted.
The Receive LAPD Controller block consists of the following sections.
The Receive LAPD Message Buffer
The Receive LAPD Controller
Each of these sections is described in some detail below.
The Receive LAPD Message Buffer
FIGURE 253. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHEN-
EVER THE
XRT79L71 HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER
MODE (WITH THE RECEIVE LAPD CONTROLLER BLOCK HIGHLIGHTED)
Receive
Payload Data
Input
Interface
Block
Receive
Payload Data
Input
Interface
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
RxSer
RxNib[3:0]
RxClk
RRING
RTIP
Receive
Overhead Data
Input Interface
Block
Receive
Overhead Data
Input Interface
Block
RxOHClk
RxOHInd
RxOH
RxOHEnable
RxOHFrame
RxNibClk
RxFrame
Rx LAPD
Controller
Block
Rx LAPD
Controller
Block
From Microprocessor
Interface Block
Rx LAPD
Buffer
(90 Bytes)
Rx LAPD
Buffer
(90 Bytes)
Rx TTM
Controller
Block
Rx TTM
Controller
Block
Rx SSM
Controller
Block
Rx SSM
Controller
Block