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XRT79L71
PRELIMINARY
531
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
It will increment the PMON P-bit/Parity Error Count Register once for each E3 frame that is determined to
have an erred EM byte. The PMON P-bit/Parity Error Count Register is located at Address = 0x1154 and
0x1155. The bit-format for each of these registers is presented below.
NOTE: For instructions on how to read out these Performance Monitor Register, please see Section 1.4.
It will also increment the One Second - P-bit/Parity Error Count - Accumulator Register once for each
incoming E3 frame that is determined to have an erred EM byte. The One Second - P-Bit/Parity Error Count
- Accumulator Register is located at Address = 0x1170 and 0x1171. The bit-format for this 16-bit register is
presented below.
NOTE: The Near-End Transmit DS3/E3 Framer block also within this particular XRT79L71 will automatically be configured
to set the FEBE/REI bit-field within the MA byte of a given outbound E3 frame to "1" for each time in which the
this transmission of the FEBE/REI indicator.
6.3.2.7
DETECTING FEBE/REI (FAR-END BLOCK ERROR/REMOTE ERROR INDICATOR) EVENTS
The Receive DS3/E3 Framer block has the responsibility for detecting and tallying the number of times that it
receives disturbed FEBE/REI indicators from the remote terminal equipment, as described below.
PMON Parity/P-Bit Error Count Register - MSB (Address = 0x1154)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_Parity_Error_Count_Upper_Byte[7:0]
RUR
0
PMON Parity/P-Bit Error Count Register - LSB (Address = 0x1155)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_Parity_Error_Count_Lower_Byte[7:0]
RUR
0
One Second - Parity Error Accumulator Register - MSB (Address = 0x1170)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
One_Second_Parity_Error_Accum_MSB[7:0]
R/O
0
One Second - Parity Error Accumulator Register - LSB (Address = 0x1171)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
One_Second_Parity_Error_Accum_LSB[7:0]
R/O
0