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XRT79L71
PRELIMINARY
413
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
TABLE 51: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE
BLOCK
SIGNAL NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION
RxSer
A5
O
Receive Serial Payload Data Output pin:
If the Receive Payload Data Output Interface block is operated in the
"Serial" Mode, then the XRT79L71 will output the payload data (that has
been extracted from the incoming E3 data-stream), via this output pin.
The XRT79L71 will update the data (on this pin) upon the rising edge of
the RxCLK output clock signal.
The user is advised to design (or configure) the System-Side Terminal
Equipment such that it will sample the data that is output via this output
pin, upon the falling edge of RxCLK.
NOTES:
1.
This signal is only active if the "NibIntf" input pin is pulled "low".
2.
In reality, for Serial Mode operation, the entire incoming E3
data-stream (payload bits and overhead bits) will be output via
the "RxSer" output pin.
The user will need to use the
"RxOHInd/RxGapClk" signals in order to distinguish the
"payload bits" from the "overhead bits" as they are output via
the "RxSer" output pin.
RxNib[3:0]
B4
A4
D6
C5
O
Receive Nibble-Parallel Payload Data Output Pin:
If the Receive Payload Data Output Interface block is operated in the
"Nibble-Parallel" Mode, then the XRT79L71 will output the payload data
(that has been extracted from the incoming E3 data-stream), via these
output pins, in a "Nibble-Parallel" manner. The XRT79L71 will update
the data (via these four output pins) upon the falling edge of the RxCLK
output signal.
The user is advised to design (or configure) the System-Side Terminal
Equipment such that it will sample this data upon the rising edge of
RxCLK.
NOTE:
These pins are only active if the "NibIntf" input pin is pulled
"high".