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XRT79L71
PRELIMINARY
227
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
The 16 bit FCS (Frame Check Sequence) is calculated over the LAPD Message Header and Information
Payload bytes, by using the CRC-16 polynomial, x16 + x12 + x5 + 1. Afterwards, this FCS value is inserted into
the two-octet FCS value position, within the LAPD Message frame. The Receive LAPD Controller block will
use the FCS bytes in order to verify that it has received a given LAPD Message in an un-erred manner. Please
see
Section 4.2.4 on how the Transmit LAPD Controller block computes and inserts the FCS values into its
outbound LAPD Message frames.
Operation of the Receive LAPD Controller
As mentioned earlier, the Receive LAPD Controller permits the user to receive either of the following basic
types of LAPD Messages.
Standard (e.g., 76 or 82 byte size) LAPD Messages
Variable Length (e.g., up to 82 byte size) LAPD Messages
The procedure for receiving these types of LAPD Messages is presented below.
4.3.3.1
Receiving Standard-type (76 or 82 byte size) LAPD Messages
The user can (1) configure the Receive LAPD Controller block to extract out the contents of the incoming
PMDL Messages from the incoming DS3 data-stream, and (2) to properly read out the contents of a newly
received message which is being stored in the Receive LAPD Message buffer, by executing the following
steps.
STEP 1 - Make sure that the XRT79L71 has been configured to operate in the C-Bit Parity Framing
format.
This is accomplished by reading out the contents of the Framer Operating Mode Register (Address = 0x1100)
and verifying that Bit 6 (DS3/E3*) is set to "1" and that Bit 2 (Frame Format) is set to "0" as illustrated below.
STEP 2 - Enable the Receive LAPD Controller
This is accomplished by setting Bit 2 (Receive LAPD Enable) within the Receive DS3 LAPD Control Register to
"1" as depicted below.
NOTES:
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local
Loop-back
DS3/E3*
Internal LOS
Enable
RESET
Direct
Mapped
ATM
Frame For-
mat
Timing Reference Select
[1:0]
R/W
X
1
X
0
X
0
X
Receive DS3 LAPD Control Register (Address = 0x1118)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLAPD
Any
Unused
Receive
LAPD
Enable
Receive
LAPD
Interrupt
Enable
Receive
LAPD
Interrupt
Status
R/W
R/O
R/W
RUR
0
1
0