![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_25.png)
PRELIMINARY
XRT79L71
10
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Figure 3 indicates that the XRT79L71 consists of the following functional blocks.
The Transmit High-Speed HDLC Controller Block
The Transmit LAPD Controller Block
The Transmit FEAC Controller Block (DS3 Applications only)
The Transmit Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications only)
The Transmit SSM Controller Block (E3, ITU-T G.832 Applications only)
The Transmit DS3/E3 Framer Block
The Transmit DS3/E3 LIU Block
The Receive DS3/E3 LIU Block
The Receive DS3/E3 Framer Block
The Receive Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications only)
The Receive SSM Controller Block (E3, ITU-T G.832 Applications only)
The Receive FEAC Controller Block (DS3 Applications only)
The Receive LAPD Controller Block
The Receive High-Speed HDLC Controller Block
Each of these functional blocks is briefly discussed below. These functional blocks will also be discussed in
considerable detail throughout this data sheet.
1.2.1
The Transmit High-Speed HDLC Controller Block
The purpose of the Transmit High-Speed HDLC Controller block is to perform the following tasks.
FIGURE 3. THE FUNCTIONAL BLOCK DIAGRAM OF THE XRT79L71 WHEN IT HAS BEEN CONFIGURED TO OPERATE IN
THE
HIGH-SPEED HDLC CONTROLLER OVER DS3/E3 MODE
Transmit
HDLC Controller
Block
Transmit DS3/E3
Framer Block
Transmit
DS3/E3
LIU Block
Transmit
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
Receive DS3/E3
Framer Block
Receive
HDLC
Controller
Block
Microprocessor
Interface
MOTO
D[7:0]
A[8:0]
IntB*
CSB*
RdB_DS
WrB_RW
Rdy_Dtck
Reset*
ALE_AS
TTIP
TRING
Tx LAPD Buffer/
Controller
Rx LAPD Buffer/
Controller
TxHDLCDat[7:0]
TxHDLCClk
SEND_MSG
SEND_FCS
RxHDLCDat[7:0]
RxHDLCClk
VAL_FCS
IDLE_FLAG
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
RRING
RTIP
Only one JA exists.
Can be configured in
Tx or Rx Path