PRELIMINARY
XRT79L71
510
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Requirements Associated with the "Local-Timing/Asynchronous" Mode
If the XRT79L71 is configured to operate in the Local-Timing/Asynchronous Mode, do the following.
Apply a 34.368MHz clock signal to the TxInClk input pin (Ball C10).
Tie the TxFrameRef input pin (Ball A11) to GND.
6.2.6.8.2
Local-Timing/TxFrameRef Mode
If the XRT79L71 is configured to operate in the Local-Timing/TxFrameRef Mode, then the following are true.
The Transmit E3 Framer block will use the clock signal that is applied to the "TxInClk" input pin as its timing
source, for generating and transmitting the outbound E3 traffic to the remote terminal equipment.
The Transmit E3 Framer block will initiate the generation (and transmission) of a new E3 frame, anytime it
detects a rising edge at the TxFrameRef input pin. In this case E3 Frame Generation (e.g., the instant
whenever the Transmit E3 Framer block begins to generate and transmit a new E3 frame) will be
synchronized to the signal that is applied to the TxFrameRef input pin.
Configuring the XRT 79L71 to operate in the Local-Timing/TxFrameRef Mode
The XRT 79L71 can be configured to operate in the Local-Timing/TxFrameRef Mode by setting Bits 1 and 0
(TimRefSel[1:0]) within the Framer Operating Mode Register to "[0, 1]" as depicted below.
Requirements Associated with the "Local-Timing/Asynchronous" Mode
If the XRT 79L71 is configured to operate in the "Local-Timing/TxFrameRef" Mode, do the following.
Apply a 34.368MHz clock signal to the TxInClk input pin (Ball C10).
Apply an 8kHz clock signal to the TxFrameRef input pin (Ball A11).
The 8kHz clock signal being applied to the TxFrameRef input pin must be synchronous with the 34.368MHz
clock signal (that is being applied to the TxInClk input pin).
6.2.6.8.3
Loop-Timing Mode
If the XRT 79L71 is configured to operate in the Loop-Timing Mode, then the following are true.
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framer
Local
Loop Back
IsDS3
Internal
LOS
Enable
RESET
Direct
Map
ATM
Frame
Format
TimRefSel[1:0]
R/W
0
1
0
1
0
1
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framer
Local
Loop Back
IsDS3
Internal
LOS
Enable
RESET
Direct
Map
ATM
Frame
Format
TimRefSel[1:0]
R/W
0
1
0
1
0
1