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PRELIMINARY
XRT79L71
268
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
TABLE 36: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK
SIGNAL NAME
PIN/
BALL #
TYPE
DESCRIPTION
TxSer
C9
I
Transmit Serial Payload Data Input Pin:
If the Transmit Payload Data Input Interface block is operated in the Serial Mode, then
the System-Side equipment is expected to apply the payload data that is to be trans-
ported via the outbound E3 data-stream to this input pin, in a serial manner. The
XRT79L71 samples the data that is on this input pin upon the rising edge of either the
RxOutClk for loop-timing applications or the TxInClk signal for local-timing applica-
tions.
NOTE: This signal is only active if the NibIntf input pin is pulled "Low".
TxNib[3:0]
B8
C8
D8
A9
I
Transmit Nibble-Parallel Payload Data Input Pins:
If the Transmit Payload Data Input Interface block is operated in the Nibble-Parallel
Mode, then the System-Side equipment is expected to apply the payload data that is
to be transported via the outbound E3 data-stream to these input pins, in a nibble-par-
allel manner. The XRT79L71 samples the data that is placed on these input pins upon
the third rising edge of TxInClk, following a given rising edge of the TxNibClk output
pin.
NOTE: These signals are only active if the NibIntf input pin is pulled "High".
TxNibFrame
A10
O
Transmit End of Frame Output Indicator - Nibble Mode:
The Transmit Section of the XRT79L71 pulses this output pin "High" for one nibble
period whenever the Transmit Payload Data Input Interface block is processing the
very last nibble within a given E3 frame. The purpose of this output pin is to alert the
System-Side Terminal Equipment that is needs to begin transmission of a new E3
frame to the Transmit Payload Data Input Interface of the XRT79L71.
NOTE: This output pin is only active if the XRT79L71 has been configured to operate
in the Nibble-Parallel Mode.
TxInClk
C10
I
Transmit Section - Timing Reference Clock Input pin:
If the XRT79L71 has been configured to operate in the Local-Timing Mode, then this
input pin will function as the timing source for the Transmit Circuitry within the
XRT79L71.
Additionally, if the XRT79L71 has been configured to operate in both the Serial and
Local-Timing Mode, then the XRT79L71 will sample the data, residing on the TxSer
input pin, upon the rising edge of this input clock signal.
TxNibClk
D9
O
Transmit Nibble-Mode Clock Output Signal:
If the XRT79L71 has been configured to operate in the Nibble-Parallel Mode, then the
XRT79L71 will derive this output clock signal from either the TxInClk or the LIU
Recovered Clock signal.
NOTE: The frequency of this clock output signal is one-fourth of the TxInClk or the
RxOutClk signals.
The user is advised to update the Nibble-Parallel data via the TxNib[3:0] output pins,
upon the rising edge of this clock output signal. The XRT79L71 will sample the
TxNib[3:0] input pins upon the third rising edge of the TxInClk clock input signal, fol-
lowing a rising edge in this particular signal.