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PRELIMINARY
XRT79L71
386
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Setting this bit-field to "0" configures the Receive E3 Framer block to declare the FERF/RDI defect condition, if
it has received at least three (3) consecutive E3 frames, in which the "A" bit-field has been set to "1".
Conversely, setting this bit-field to "1" configures the Receive E3 Framer block to declare the FERF/RDI defect
condition, if it has received at least five (5) consecutive E3 frames, in which the FERF/RDI bit-field has been
set to "1".
When the Receive E3 Framer block declares the "FERF" or "RDI" defect condition in the incoming E3 frame,
then it will then do the following.
It will set Bit 0 (FERF/RDI Defect Declared), within the Receive E3 Configuration and Status Register # 2" to
"1" as depicted below.
This bit-field will remain asserted for the duration that the Receive E3 Framer block declares the FERF/RDI
defect condition.
The Receive E3 Framer block will also generate the "Change in FERF/RDI Defect Condition" Interrupt
request, by asserting the Interrupt Output pin (e.g., by pulling it "LOW") and setting Bit 3 (Change in FERF/
RDI Defect Condition Interrupt Status), within the Receive E3 Interrupt Status Register # 2" to "1" as depicted
below.
5.3.2.5.3
Clearing the FERF/RDI Defect Condition
Receive E3 Configuration and Status Register # 1 - G.751 (Address = 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RxFERF
Algo
Unused
RxBIP-4
Enable
R/O
R/W
R/O
R/W
0
X
0
Receive E3 Configuration and Status Register # 2 - G.751 (Address = 0x1111)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
LOF
Algo
LOF
Defect
Condition
Declared
OOF
Defect
Condition
Declared
LOS
Defect
Condition
Declared
AIS Defect
Condition
Declared
Unused
FERF/RDI
Defect
Condition
Declared
R/W
R/O
X
0
1
Receive E3 Interrupt Status Register # 2 - G.751 (Address = 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of
FERF/RDI
Defect
Condition
Interrupt
Status
Detection of
BIP-4
Error
Interrupt
Status
Detection of
FAS Bit
Error
Interrupt
Status
Reserved
R/O
RUR
R/O
0
1
0