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XRT79L71
PRELIMINARY
467
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
assertion period, it can decide when to insert the appropriate bit-value to the Transmit Overhead Data Input
Interface block and in-turn, force the Transmit DS3/E3 Framer block to insert this bit into the appropriate
overhead bit-position within the outbound E3 data-stream.
From all of this, the System-Side Terminal
Equipment will know when it should assert the TxOHIns input pin and place the appropriate value on the TxOH
input pin of the XRT79L71.
Table 61 relates the number of TxOHEnable output pulses that have occurred since both the TxOHFrame and
the TxOHEnable pins were both sampled "High", to the E3 Overhead bit being processed by the Transmit
Overhead Data Input Interface block. The user can use this table as a guide for inserting the appropriate
overhead bits, within the outbound E3 data-stream for Method 2.
TABLE 61: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE TXOHENABLE SIGNAL, SINCE THE
TXOHFRAME SIGNAL WAS LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS CURRENTLY BEING PROCESSED
BY THE
TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK
NUMBER OF PULSES IN TXOHENABLE,
SINCE
TXOHFRAME BEING SAMPLED
"HIGH"
THE OVERHEAD BIT TO BE PROCESSED
BY THE
TRANSMIT OVERHEAD DATA INPUT
INTERFACE BLOCK
CAN THIS OVERHEAD BIT BE ACCEPTED
BY THE
XRT79L71, AND INSERTED INTO
THE OUTBOUND
E3 DATA-STREAM?
0 (TxOHEnable and TxOHFrame are
sampled "High" simultaneously)
FA1 Byte, Bit 1 (MSB)
NO
1
FA1 Byte, Bit 2
NO
2
FA1 Byte, Bit 3
NO
3
FA1 Byte, Bit 4
NO
4
FA1 Byte, Bit 5
NO
5
FA1 Byte, Bit 6
NO
6
FA1 Byte, Bit 7
NO
7
FA1 Byte, Bit 8 (LSB)
NO
8
FA2 Byte, Bit 1 (MSB)
NO
9
FA2 Byte, Bit 2
NO
10
FA2 Byte, Bit 3
NO
11
FA2 Byte, Bit 4
NO
12
FA2 Byte, Bit 5
NO
13
FA2 Byte, Bit 6
NO
14
FA2 Byte, Bit 7
NO
15
FA2 Byte, Bit 8 (LSB)
NO
16
EM Byte, Bit 1 (MSB)
NO
17
EM Byte, Bit 2
NO
18
EM Byte, Bit 3
NO
19
EM Byte, Bit 4
NO
20
EM Byte, Bit 5
NO
21
EM Byte, Bit 6
NO
22
EM Byte, Bit 7
NO