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參數(shù)資料
| 型號： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 96/198頁 |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
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Spartan-3 FPGA Family: Pinout Descriptions
10
www.xilinx.com
DS099-4 (v1.6) January 17, 2005
Product Specification
R
JTAG Configuration Mode
In the JTAG configuration mode all dual-purpose configura-
tion pins are unused and behave exactly like user-I/O pins,
as shown in
Table 10
. See
Table 7
for Mode Select pin set-
tings required for JTAG mode.
Dual-Purpose Pin I/O Standard During Configura-
tion
During configuration, the dual-purpose pins default to
CMOS input and output levels for the associated VCCO
voltage supply pins. For example, in the Parallel configura-
tion modes, both VCCO_4 and VCCO_5 are required. If
connected to +2.5V, then the associated pins conform to the
LVCMOS25 I/O standard. If connected to +3.3V, then the
pins drive LVCMOS output levels and accept either LVTTL
or LVCMOS input levels.
Dual-Purpose Pin Behavior After Configuration
After the configuration process completes, these pins, if
they were borrowed during configuration, become user-I/O
pins available to the application. If a dual-purpose configu-
ration pin is not used during the configuration process—
i.e.
,
the parallel configuration pins when using serial
mode—then the pin behaves exactly like a general-purpose
I/O. See
I/O Type: Unrestricted, General-purpose I/O
Pins
section above.
RDWR_B
Input
Read/Write Control for Parallel Mode Configuration:
In Master and Slave Parallel modes, assert this pin Low together with CS_B to write a
configuration data byte from the D0-D7 bus to the FPGA on a rising CCLK edge. Once
asserted during configuration, RDWR_B must remain asserted until configuration is
complete.
During Readback, assert this pin High with CS_B Low to read a configuration data byte from
the FPGA to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
BUSY
Output
Configuration Data Rate Control for Parallel Mode:
In the Slave and Master Parallel modes, BUSY throttles the rate at which configuration data
is loaded. BUSY is only necessary if CCLK operates at greater than 50 MHz. Ignore BUSY
for frequencies of 50 MHz and below.
When BUSY is Low, the FPGA accepts the next configuration data byte on the next rising
CCLK edge for which CS_B and RDWR_B are Low. When BUSY is High, the FPGA ignores
the next configuration data byte. The next configuration data value must be held or reloaded
until the next rising CCLK edge when BUSY is Low. When CS_B is High, BUSY is in a high
impedance state.
This signal is located in Bank 4 and its output voltage is determined by VCCO_4. The BitGen
option Persist permits this pin to retain its configuration function in the User mode.
INIT_B
Bidirectional
(open-drain)
Initializing Configuration Memory/Configuration Error (active-Low):
See description under
Serial Configuration Modes
, page 7
.
Table 4:
Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes
(Continued)
Pin
Name
Direction
Description
RDWR_B
Function
0
If CS_B is Low, then load (write) configuration data to the FPGA.
1
This option is valid only if the Persist bitstream option is set to Yes. If CS_B is
Low, then read configuration data from the FPGA.
BUSY
Function
0
The FPGA is ready to accept the next configuration data byte.
1
The FPGA is busy processing the current configuration data byte and is not
ready to accept the next byte.
Hi-Z
If CS_B is High, then BUSY is high impedance.
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