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| 型號： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 81/198頁 |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
Spartan-3 FPGA Family: DC and Switching Characteristics
34
www.xilinx.com
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
R
Configuration and JTAG Timing
Figure 5:
Waveforms for Power-On and the Beginning of Configuration
Table 34:
Power-On Timing and the Beginning of Configuration
Symbol
T
POR(2)
Description
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
All Speed Grades
Min
-
-
-
-
-
-
-
-
0.3
-
-
-
-
-
-
-
-
0.5
Units
ms
ms
ms
ms
ms
ms
ms
ms
μ
s
ms
ms
ms
ms
ms
ms
ms
ms
μ
s
Max
5
5
5
5
7
7
7
7
-
2
2
2
2
3
3
3
3
4.0
The time from the application of V
CCINT
, V
CCAUX
, and V
CCO
Bank 4 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
T
PROG
T
PL(2)
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
T
ICCK(3)
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
Notes:
1.
The numbers in this table are based on the operating conditions set forth in
Table 5
. This means power must be applied to all V
CCINT
,
V
CCO
, and V
CCAUX
lines.
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only for the Master Serial and Master Parallel modes.
2.
3.
V
CCINT
(Supply)
(Supply)
(Supply)
V
CCAUX
V
CCO
Bank 4
PROG_B
(Input)
(Output)
(Open-Drain)
INIT_B
CCLK
DS099-3_03_120604
1.2V
2.5V
T
ICCK
T
PROG
T
PL
T
POR
1.0V
1.0V
2.0V
Notes:
1.
2.
3.
The V
CCINT
, V
CCAUX
, and V
CCO
supplies may be applied in any order.
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
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