- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄374986 > XC3S1000 (Xilinx, Inc.) Spartan-3 FPGA Family: Complete Data Sheet PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3S1000 |
| 廠(chǎng)商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 19/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)
Spartan-3 FPGA Family: Functional Description
12
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry chain enters the slice as CIN
and exits as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the lower portion as well as
CY0G and CYMUXG in the upper portion. The dedicated
arithmetic logic includes the exclusive-OR gates XORF and
XORG (upper and lower portions of the slice, respectively)
as well as the AND gates GAND and FAND (upper and
lower portions, respectively).
Main Logic Paths
Central to the operation of each slice are two nearly identi-
cal data paths, distinguished using the terms
top
and
bot-
tom
. The description that follows uses names associated
with the bottom path. (The top path names appear in paren-
theses.) The basic path originates at an interconnect-switch
matrix outside the CLB. Four lines, F1 through F4 (or G1
through G4 on the upper path), enter the slice and connect
directly to the LUT. Once inside the slice, the lower 4-bit
path passes through a function generator "F" (or "G") that
performs logic operations. The function generator’s Data
output, "D", offers five possible paths:
1.
Exit the slice via line "X" (or "Y") and return to
interconnect.
2.
Inside the slice, "X" (or "Y") serves as an input to the
DXMUX (DYMUX) which feeds the data input, "D", of
the FFY (FFX) storage element. The "Q" output of the
storage element drives the line XQ (or YQ) which exits
the slice.
3.
Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
4.
With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on "X" (or "Y").
5.
Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The "D" outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
BY in the top half) can take any of several possible
branches:
1.
Bypass both the LUT and the storage element, then exit
the slice as BXOUT (or BYOUT) and return to
interconnect.
2.
Bypass the LUT, then pass through a storage element
via the D input before exiting as XQ (or YQ).
3.
Control the wide function multiplexer F5MUX (or
F6MUX).
4.
Via multiplexers, serve as an input to the carry chain.
5.
6.
Drives the DI input of the LUT.
BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Section.
Finally, the DIG_MUX multiplexer can switch BY onto to
the DIG line, which exits the slice.
Other slice signals shown in
Figure 6, page 11
are dis-
cussed in the sections that follow.
7.
Function Generator
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). This permits any
four-variable Boolean logic operation to be programmed
into them. Furthermore, wide function multiplexers can be
used to effectively combine LUTs within the same CLB or
across different CLBs, making logic functions with still more
input variables possible.
The LUTs in both the right-hand and left-hand slice-pairs
not only support the logic functions described above, but
also can function as ROM that is initialized with data at the
time of configuration.
The LUTs in the left-hand slice-pair (even-numbered col-
umns such as X0 in
Figure 5
) of each CLB support two
additional functions that the right-hand slice-pair (odd-num-
bered columns such as X1) do not.
First, it is possible to program the “l(fā)eft-hand LUTs” as dis-
tributed RAM. This type of memory affords moderate
amounts of data buffering anywhere along a data path. One
left-hand LUT stores 16 bits. Multiple left-hand LUTs can be
combined in various ways to store larger amounts of data. A
dual port option combines two LUTs so that memory access
is possible from two independent data lines. A Distributed
ROM option permits pre-loading the memory with data dur-
ing FPGA configuration.
Second, it is possible to program each left-hand LUT as a
16-bit shift register. Used in this way, each LUT can delay
serial data anywhere from one to 16 clock cycles. The four
left-hand LUTs of a single CLB can be combined to produce
delays up to 64 clock cycles. The SHIFTIN and SHIFTOUT
lines cascade LUTs to form larger shift registers. It is also
possible to combine shift registers across more than one
CLB. The resulting programmable delays can be used to
balance the timing of data pipelines.
Block RAM Overview
All Spartan-3 devices support block RAM, which is orga-
nized as configurable, synchronous 18Kbit blocks. Block
RAM stores relatively large amounts of data more efficiently
than the distributed RAM feature described earlier. (The lat-
ter is better suited for buffering small amounts of data any-
where along signal paths.) This section describes basic
Block RAM functions. For more information, see
XAPP463
:
Using Block RAM in Spartan-3 FPGAs
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CP132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4CPG132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。