- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374986 > XC3S1000 (Xilinx, Inc.) Spartan-3 FPGA Family: Complete Data Sheet PDF資料下載
參數(shù)資料
| 型號： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 17/198頁 |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁
Spartan-3 FPGA Family: Functional Description
10
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
.
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four intercon-
nected slices, as shown in
Figure 5
. These slices are
grouped in pairs. Each pair is organized as a column with an
independent carry chain.
The nomenclature that the FPGA Editor — part of the Xilinx
development software — uses to designate slices is as fol-
lows: The letter "X" followed by a number identifies columns
of slices. The "X" number counts up in sequence from the
left side of the die to the right. The letter "Y" followed by a
number identifies the position of each slice in a pair as well
as indicating the CLB row. The "Y" number counts slices
starting from the bottom of the die according to the
sequence: 0, 1, 0, 1 (the first CLB row); 2, 3, 2, 3 (the sec-
ond CLB row); etc.
Figure 5
shows the CLB located in the
lower left-hand corner of the die. Slices X0Y0 and X0Y1
make up the column-pair on the left where as slices X1Y0
and X1Y1 make up the column-pair on the right. For each
CLB, the term “l(fā)eft-hand” (or SLICEM) is used to indicated
the pair of slices labeled with an even "X" number, such as
X0, and the term “right-hand” (or SLICEL) designates the
pair of slices with an odd "X" number, e.g., X1.
Elements Within a Slice
All four slices have the following elements in common: two
logic function generators, two storage elements, wide-func-
tion multiplexers, carry logic, and arithmetic gates, as
shown in
Figure 6
. Both the left-hand and right-hand slice
pairs use these elements to provide logic, arithmetic, and
ROM functions. Besides these, the left-hand pair supports
two additional functions: storing data using Distributed RAM
and shifting data with 16-bit registers.
Figure 6
is a diagram
of the left-hand slice; therefore, it represents a superset of
the elements and connections to be found in all slices. See
Function Generator
, page 12
for more information.
The RAM-based function generator — also known as a
Look-Up Table or LUT — is the main resource for imple-
menting logic functions. Furthermore, the LUTs in each
left-hand slice pair can be configured as Distributed RAM or
a 16-bit shift register. For information on the former, see
XAPP464
:
Using Look-Up Tables as Distributed RAM in
Spartan-3 FPGAs
; for information on the latter, refer to
XAPP465
:
Using Look-Up Tables as Shift Registers (SRL16)
in Spartan-3 FPGAs
. The function generators located in the
upper and lower portions of the slice are referred to as the
"G" and "F", respectively.
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive latch, provides a means
for synchronizing data to a clock signal, among other uses.
The storage elements in the upper and lower portions of the
slice are called FFY and FFX, respectively.
Wide-function multiplexers effectively combine LUTs in
order to permit more complex logic operations. Each slice
has two of these multiplexers with F5MUX in the lower por-
tion of the slice and FXMUX in the upper portion. Depend-
ing on the slice, FXMUX takes on the name F6MUX,
F7MUX, or F8MUX. For more details on the multiplexers,
see
XAPP466
:
Using Dedicated Multiplexers in Spartan-3
FPGAs
.
Figure 5:
Arrangement of Slices within the CLB
DS099-2_05_082104
Interconnect
to Neighbors
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
CIN
SLICE
X0Y1
SLICE
X0Y0
Switch
Matrix
COUT
CLB
COUT
SHIFTOUT
SHIFTIN
CIN
SLICE
X1Y1
SLICE
X1Y0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CP132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4CPG132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。