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參數(shù)資料
| 型號(hào)： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 20/198頁 |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
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Spartan-3 FPGA Family: Functional Description
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
www.xilinx.com
13
R
The aspect ratio — i.e., width vs. depth — of each block
RAM is configurable. Furthermore, multiple blocks can be
cascaded to create still wider and/or deeper memories.
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAM16_S[w
A
]_S[w
B
] calls out the dual-port primi-
tive, where the integers w
A
and w
B
specify the total data
path width at ports w
A
and w
B
, respectively. Thus, a
RAM16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A
and an 18-bit-wide Port B. A name of the form RAM16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port. A
RAM16_S18 is a single-port RAM with an 18-bit-wide port.
Other memory functions — e.g., FIFOs, data path width
conversion, ROM, etc. — are readily available using the
CORE Generator system, part of the Xilinx development
software.
Arrangement of RAM Blocks on Die
The XC3S50 has one column of block RAM. The Spartan-3
devices ranging from the XC3S200 to XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000
have four columns. The position of the columns on the die is
shown in
Figure 1
in Module 1:
Introduction and Ordering
Information
. For a given device, the total available RAM
blocks are distributed equally among the columns.
Table 8
shows the number of RAM blocks, the data storage capac-
ity, and the number of columns for each device.
Block RAM and multipliers have interconnects between
them that permit simultaneous operation; however, since
the multiplier shares inputs with the upper data bits of block
RAM, the maximum data path width of the block RAM is 18
bits in this case.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common RAM block, which has a maximum capacity of
18,432 bits — or 16,384 bits when no parity lines are used.
Each port has its own dedicated set of data, control and
clock lines for synchronous read and write operations.
There are four basic data paths, as shown in
Figure 7
: (1)
write to and read from Port A, (2) write to and read from Port
B, (3) data transfer from Port A to Port B, and (4) data trans-
fer from Port B to Port A.
Block RAM Port Signal Definitions
Representations
of
RAM16_S[w
A
]_S[w
B
]
RAM16_S[w] with their associated signals are shown in
Figure 8a
and
Figure 8b
, respectively. These signals are
defined in
Table 9
.
the
dual-port
single-port
primitive
primitive
and
the
Table 8:
Number of RAM Blocks by Device
Device
Total Number
of RAM Blocks
Total
Addressable
Locations (bits)
Number
of
Columns
XC3S50
4
73,728
1
XC3S200
12
221,184
2
XC3S400
16
294,912
2
XC3S1000
24
442,368
2
XC3S1500
32
589,824
2
XC3S2000
40
737,280
2
XC3S4000
96
1,769,472
4
XC3S5000
104
1,916,928
4
Figure 7:
Block RAM Data Paths
DS099-2_12_030703
Spartan-3
Dual Port
Block RAM
Read 3
Read
Write
Write
Read
Write
Write
Read
P
P
2
1
4
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| XC3S1000-4CP132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
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