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參數(shù)資料
| 型號(hào)： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊(cè) |
| 文件頁數(shù)： | 40/198頁 |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
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Spartan-3 FPGA Family: Functional Description
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
www.xilinx.com
33
R
3.3V-Tolerant Configuration Interface
It is possible to achieve 3.3V-tolerance at the configuration
interface simply by adding a few external resistors. This
approach may prove useful when it is undesirable to switch
the VCCO_4 and VCCO_5 voltages from 2.5V to 3.3V after
configuration.
The 3.3V-tolerance is implemented as follows (a similar
approach can be used for other supply voltage levels):
First, to power the Dual-Purpose configuration pins, apply
3.3V to the VCCO_4 and (as needed) the VCCO_5 lines.
This scales the output voltages and input thresholds associ-
ated with these pins so that they become 3.3V-compatible.
Second, to power the Dedicated configuration pins, apply
2.5V to the V
CCAUX
lines (the same as for the standard
interface). In order to achieve 3.3V-tolerance, the Dedicated
inputs will require series resistors that limit the incoming
current to 10mA or less. The Dedicated outputs will need
pull-up resistors to ensure adequate noise margin when the
FPGA is driving a High logic level into another device’s 3.3V
receiver. Choose a power regulator or supply that can toler-
ate reverse current on the V
CCAUX
lines.
Configuration Modes
Spartan-3 supports the following five configuration modes:
Slave Serial mode
Master Serial mode
Slave Parallel
mode
Master Parallel mode
Boundary-Scan (JTAG) mode (IEEE 1532/IEEE
1149.1)
Slave Serial Mode
In Slave Serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The FPGA on the far right of
Figure 20
is set for the Slave Serial mode. The CCLK pin on the FPGA
is an input in this mode. The serial bitstream must be set up
at the DIN input pin a short time before each rising edge of
the externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the falling
edge of CCLK.
Figure 20:
Connection Diagram for Master and Slave Serial Configuration
DOUT
DIN
CCLK
DONE
INIT_B
Spartan-3
FPGA
Master
PROG_B
DIN
CCLK
DONE
INIT_B
Spartan-3
FPGA
Slave
PROG_B
DS099_23_041103
D0
CLK
CE
OE/RESET
CF
Platform
Flash PROM
XCF0xS
or
XCFxxP
V
CCINT
1.2V
V
CCAUX
V
CCO
Bank 4
2.5V
2.5V
4.7K
All
2.5V
V
CCAUX
V
CCINT
V
CCO
Bank 4
1.2V
3.3V
V
CC
V
CCJ
V
CCO
2.5V
2.5V
M0
M1
M2
M0
M1
M2
GND
GND
GND
Notes:
1.
There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the
last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This enables
the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining
FPGAs in the chain. Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain
and require the pull-up resistor shown in grey. In most cases, a value between 3.3K
to 4.7K
is sufficient.
However, when using DONE synchronously with a long chain of FPGAs, cumulative capacitance may
necessitate lower resistor values (e.g. down to 330
) in order to ensure a rise time within one clock cycle.
For information on how to program the FPGA using 3.3V signals and power, see
3.3V-Tolerant Configuration
Interface
.
2.
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