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參數(shù)資料
| 型號(hào)： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 90/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
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Spartan-3 FPGA Family: Pinout Descriptions
4
www.xilinx.com
DS099-4 (v1.6) January 17, 2005
Product Specification
R
IO_Lxxy_#/INIT_B
Bidirectional (open-drain)
during configuration
User I/O after configuration
Initializing Configuration Memory/Detected Configuration Error:
When Low, this pin indicates that configuration memory is being
cleared. When held Low, this pin delays the start of configuration.
After this pin is released or configuration memory is cleared, the
pin goes High. During configuration, a Low on this output indicates
that a configuration data error occurred. This pin becomes a user
I/O after configuration.
DCI:
Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/VRN_# or
IO/VRN_#
Input when using DCI
Otherwise, same as I/O
DCI Reference Resistor for NMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is
connected between this pin and the VCCO supply for this bank.
Otherwise, this pin is a user I/O.
IO_Lxxy_#/VRP_# or
IO/VRP_#
Input when using DCI
Otherwise, same as I/O
DCI Reference Resistor for PMOS I/O Transistor (per bank):
If using DCI, a 1% precision impedance-matching resistor is
connected between this pin and the ground supply. Otherwise, this
pin is a user I/O.
GCLK:
Global clock buffer inputs
IO_Lxxy_#/GCLK0,
IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2,
IO_Lxxy_#/GCLK3,
IO_Lxxy_#/GCLK4,
IO_Lxxy_#/GCLK5,
IO_Lxxy_#/GCLK6,
IO_Lxxy_#/GCLK7
Input if connected to global
clock buffers
Otherwise, same as I/O
Global Buffer Input:
Direct input to a low-skew global clock buffer. If not connected to a
global clock buffer, this pin is a user I/O.
VREF:
I/O bank input reference voltage pins
IO_Lxxy_#/VREF_#
or
IO/VREF_#
Voltage supply input when
VREF pins are used within a
bank.
Otherwise, same as I/O
Input Buffer Reference Voltage for Special I/O Standards (per
bank):
If required to support special I/O standards, all the VREF pins
within a bank connect to a input threshold voltage source.
If not used as input reference voltage pins, these pins are available
as individual user-I/O pins.
CONFIG:
Dedicated configuration pins
CCLK
Input in Slave configuration
modes
Output in Master
configuration modes
Configuration Clock:
The configuration clock signal synchronizes configuration data.
PROG_B
Input
Program/Configure Device:
Active Low asynchronous reset to configuration logic. Asserting
PROG_B Low for an extended period delays the configuration
process. This pin has an internal weak pull-up resistor during
configuration.
Table 2:
Spartan-3 Pin Definitions
(Continued)
Pin Name
Direction
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CP132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4CPG132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
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