- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄374986 > XC3S1000 (Xilinx, Inc.) Spartan-3 FPGA Family: Complete Data Sheet PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3S1000 |
| 廠(chǎng)商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 60/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
39
www.xilinx.com
13
R
Table 14:
Pin-to-Pin Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
Device
Speed Grade
-5
Min
Units
-4
Min
Setup Times
T
PSDCM
When writing to the Input
Flip-Flop (IFF), the time
from the setup of data at the
Input pin to the active
transition at a Global Clock
pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25
(2)
,
IOBDELAY = NONE,
with DCM
(4)
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
2.37
2.71
ns
2.13
2.35
ns
2.15
2.36
ns
2.58
2.95
ns
2.55
2.91
ns
2.59
2.96
ns
2.67
3.05
ns
2.52
2.88
ns
T
PSFD
When writing to IFF, the
time from the setup of data
at the Input pin to an active
transition at the Global
Clock pin. The DCM is not
in use. The Input Delay is
programmed.
LVCMOS25
(2)
,
IOBDELAY = IFD,
without DCM
3.00
3.46
ns
2.63
3.02
ns
2.50
2.87
ns
3.50
4.03
ns
3.78
4.35
ns
3.78
4.35
ns
4.44
5.12
ns
5.26
6.06
ns
Hold Times
T
PHDCM
When writing to IFF, the
time from the active
transition at the Global
Clock pin to the point when
data must be held at the
Input pin. The DCM is in
use. No Input Delay is
programmed.
LVCMOS25
(3)
,
IOBDELAY = NONE,
with DCM
(4)
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
–0.45
–0.40
ns
–0.12
–0.05
ns
–0.12
–0.05
ns
–0.43
–0.38
ns
–0.45
–0.40
ns
–0.47
–0.42
ns
–0.54
–0.49
ns
–0.49
–0.44
ns
T
PHFD
When writing to IFF, the
time from the active
transition at the Global
Clock pin to the point when
data must be held at the
Input pin. The DCM is not in
use. The Input Delay is
programmed.
LVCMOS25
(3)
,
IOBDELAY = IFD,
without DCM
–0.98
–0.93
ns
–0.40
–0.35
ns
–0.27
–0.22
ns
–1.19
–1.14
ns
–1.43
–1.38
ns
–1.38
–1.33
ns
–1.82
–1.77
ns
–2.57
–2.52
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in
Table 21
and are based on the operating conditions set
forth in
Table 5
and
Table 8
.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input,
subtract
the appropriate adjustment from
Table 17
. If this is true of the data Input,
add
the appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input,
add
the appropriate Input adjustment from
Table 17
. If this is true of the data Input,
subtract
the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data
before the clock’s active edge.
DCM output jitter is included in all measurements.
2.
3.
4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQ208C | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4CP132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CP132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4CPG132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4CPG132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4FG1156C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。