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參數(shù)資料
| 型號(hào)： | XC3S1000 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | 的Spartan - 3 FPGA系列：完整的數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 43/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000 |
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Spartan-3 FPGA Family: Functional Description
36
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
Master Parallel Mode
In this mode, the device is configured byte-wide on a CCLK
supplied by the FPGA. Timing is similar to the Slave Parallel
mode except that CCLK is supplied by the FPGA. The
device connections are shown in
Figure 22
.
Boundary-Scan (JTAG) Mode
In Boundary-Scan mode, dedicated pins are used for con-
figuring the FPGA. The configuration is done entirely
through the IEEE 1149.1 Test Access Port (TAP). FPGA
configuration using the Boundary-Scan mode is compliant
with the IEEE 1149.1-1993 standard and the new IEEE
1532 standard for In-System Configurable (ISC) devices.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
Boundary-Scan mode simply turns off the other modes.
Configuration Sequence
The configuration of Spartan-3 devices is a three-stage pro-
cess that occurs after Power-On Reset or the assertion of
PROG_B. POR occurs after the V
CCINT
, V
CCAUX
, and V
CCO
Bank 4 supplies have reached their respective maximum
input threshold levels (see
Table 6
in Module 3:
DC and
Switching Characteristics
). After POR, the three-stage
process begins.
First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process. A flow diagram for
the configuration sequence of the Serial and Parallel modes
is shown in
Figure 23
. The flow diagram for the Bound-
ary-Scan configuration sequence appears in
Figure 24
.
Figure 22:
Connection Diagram for Master Parallel Configuration
Spartan-3
Master
D[0:7]
CCLK
PROG_B
DONE
INIT_B
DATA[0:7]
CCLK
RDWR_B
CS_B
CF
CE
OE/RESET
Platform Flash
PROM
XCFxxP
DS099_25_041103
2.5V
V
CCAUX
V
CCO
Banks 4 & 5
V
CCINT
1.2V
GND
GND
3.3V
V
CC
V
CCJ
V
CCO
2.5V
2.5V
All
4.7K
Notes:
1.
There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes"
only for the last FPGA to be configured in the chain shown above (or for the single FPGA as may be
the case). This enables the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone
is set to "No" for the remaining FPGAs in the chain. Second, DriveDone can be set to "No" for all
FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in grey. In most
cases, a value between 3.3K
to 4.7K
is sufficient. However, when using DONE synchronously
with a long chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g.
down to 330
) in order to ensure a rise time within one clock cycle.
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