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參數(shù)資料
| 型號(hào)： | uPSD3233 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器) |
| 中文描述： | 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器） |
| 文件頁(yè)數(shù)： | 98/164頁(yè) |
| 文件大?。?/td> | 1133K |
| 代理商： | UPSD3233 |
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μ
PSD3200 FAMILY
98/164
DRAFT(Thursday 20 June 2002, 13:15).
Instructions
An instruction consists of a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD Module and not executed as a
standard Write operation. The instruction is exe-
cuted when the correct number of bytes are prop-
erly
received
and
the
consecutive bytes is shorter than the time-out pe-
riod. Some instructions are structured to include
Read operations after the initial Write operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The Flash memory supports the instructions sum-
marized in Table 83:
Flash memory:
I
Erase memory by chip or sector
I
Suspend or resume sector erase
I
Program a Byte
time
between
two
I
Reset to Read mode
I
Read primary Flash Identifier value
I
Read Sector Protection Status
I
Bypass
These instructionsare detailed in Table 83.For ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-
cle. Address signals A15-A12 are Don’t Care dur-
ing the instruction Write cycles. However, the
appropriate
Sector
Select
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memoryis selected
if
any
one
of
Sector
CSBOOT3) is High.
Power-down Instruction and Power-up Mode
Power-up Mode.
The PSD Module internal logic
is reset upon Power-up to the Read mode. Sector
Select
(FS0-FS7
and
must be held Low, and Write Strobe (WR, CNTL0)
High, during Power-up for maximum security of
the data contents and to remove the possibility of
a byte being written on the first edge of Write
(FS0-FS7
or
Select
(CSBOOT0-
CSBOOT0-CSBOOT3)
Strobe (WR, CNTL0). Any Write cycle initiation is
locked when V
CC
is below V
LKO
.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using Read operations just as it would a
ROM or RAM device. Alternately, the MCU may
use Read operations to obtain status information
about a Program or Erase cycle that is currentlyin
progress. Lastly, theMCU mayuse instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents.
Primary Flash memory
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 83). The MCU can
read the memory contents of the primary Flash
memory or the secondary Flash memory by using
Read operations any time the Read operation is
not part of an instruction.
Read Primary Flash Identifier.
The
Flash memory identifier (E7h) is read with an in-
struction composed of 4 operations: 3 specific
Write operations and a Read operation (see Table
83). During the Read operation, address bits A6,
A1, and A0 must be 0,0,1, respectively, and the
appropriate Sector Select (FS0-FS7) must be
High.
Read Memory Sector Protection Status.
The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific Write operations and a Read operation
(see Table 83). During the Read operation, ad-
dress bits A6, A1, and A0 must be 0,1,0, respec-
tively,
while
Sector
CSBOOT0-CSBOOT3)
memory sector whose protection has to be veri-
fied.The Read operation produces 01h if theFlash
memory sector is protected, or 00h if the sector is
not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem-
ory) can also be read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro-
tect”, on page 103, for register definitions.
Reading the Erase/Program Status Bits.
The
Flash memory provides several status bits to be
used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These
status bits minimize the timethat theMCU spends
performing these tasks and are defined in Table
84. The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instructionis being executedby
primary
Select
designates
(FS0-FS7
the
or
Flash
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3233A-24T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233A-24T1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233A-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233A-24T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233A-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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