參數(shù)資料
型號(hào): uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 51/164頁
文件大小: 1133K
代理商: UPSD3233
51/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
the serial port as a baud rate generator, or in fact,
in any application not requiring an interrupt.
Timer 2
Like timer 0 and 1, timer2 can operateas eitheran
event timer or as an event counter. This is select-
ed by bit C/T2 in the special function register
T2CON. It has three operating modes: capture,
autoload, and baud rate generator, which are se-
lected bybits in the T2CON as shown in Table 41.
In the Capture Mode there are two options which
are selected by bit EXEN2 in T2CON. if EXEN2 =
0, then Timer 2 is a 16-bit timer or counter which
upon overflowing sets bit TF2, the Timer 2 over-
flow bit, which can be used to generate an inter-
rupt. If EXEN2 = 1, then Timer 2 still does the
above, but with the added feature that a 1-to-0
transition at external input T2EX causes the cur-
rent value in the Timer 2 registers, TL2 and TH2,
to be captured into registers RCAP2L and
RCAP2H, respectively. In addition, the transition
at T2EX causes bit EXF2 in T2CON to be set, and
EXF2 likeTF2 cangeneratean interrupt. The Cap-
ture Mode is illustrated in Figure 24.
In the auto-reload mode, there are again two op-
tions, which are selected by bit EXEN2 in T2CON.
If EXEN2 = 0, then when Timer 2 rolls over it not
only sets TF2 but also causes the Timer 2 regis-
ters to be reloaded with the 16-bit value in regis-
ters RCAP2L and RCAP2H, which are preset by
software. If EXEN2 = 1, then Timer 2 still does the
above, but with the added feature that a 1-to-0
transition at external input T2EX will also trigger
the 16-bit reload and set EXF2. The auto-reload
mode is illustrated in Standard Serial Interface
(UART) Figure 25. The baudrate generationmode
is selected by (RCLK, RCLK1)=1 and/or (TCLK,
TCLK1)=1. It will be described in conjunction with
the serial port.
Table 40. Timer/Counter2 Control Register (T2CON)
Table 41. Description of the T2CON Bits
Note: 1. The RCLK1 and TCLK1 bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Bit
Symbol
Function
7
TF2
Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by software. TF2
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1
6
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software
5
RCLK
1
Receive clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the receive clock
4
TCLK
1
Transmit clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the transmit clock
3
EXEN2
Timer 2external enable flag. When set, allows a capture orreload to occur as a result of
a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX
2
TR2
Start/stop control for Timer 2. A logic 1 starts the timer
1
C/T2
Timer or Counter select for Timer 2. Cleared for timer operation (input from internal
system clock, t
CPU
); set for external event counter operation (negative edge triggered)
0
CP/RL2
Capture/reload flag. When set, capture will occur on negative transition of T2EX if
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow
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