參數(shù)資料
型號(hào): uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 62/164頁
文件大小: 1133K
代理商: UPSD3233
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PSD3200 FAMILY
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DRAFT(Thursday 20 June 2002, 13:15).
ANALOG-TO-DIGITAL CONVERTOR (ADC)
The analog to digital (A/D) converter allows con-
version of an analog input to a corresponding 8-bit
digital value. The A/D module has four analog in-
puts, which are multiplexed into one sample and
hold. The output of the sample and hold is the in-
put into the converter, which generates the result
via successive approximation. The analog supply
voltage is connected to AVREF of ladder resis-
tance of A/D module.
The A/D module has two registers which are the
control register ACON and A/D result register
ADAT. The register ACON, shown in Table 46,
controls the operation of the A/D converter mod-
ule. To use analog inputs, I/O is selected by
P1SFS register. Also an 8-bit prescaler ASCL di-
vides themain system clock input down to approx-
imately 6 MHz clock that is required for the ADC
logic. Appropriate values need to be loaded into
the prescaler basedupon the main MCU clock fre-
quency prior to use.
The processing of conversion starts when the start
bit ADST is set to 1. After one cycle, it is cleared
by hardware. The register ADAT contains the re-
sults of the A/D conversion. When conversion is
completed, the result is loaded into the ADAT the
A/D conversion status bit ADSF is set to 1.
The block diagram of the A/D module is shown in
Figure 34. TheA/D status bit ADSF isset automat-
ically when A/D conversion is completed, cleared
when A/D conversion is in process.
Figure 34. A/D Block Diagram
Table 45. ADC SFR Memory Map
SFR
Addr
Reg
Name
Bit Register Name
ValueComments
7
6
5
4
3
2
1
0
95
ASCL
00
8-bit
Prescaler for
ADC clock
96
ADAT
ADAT7
ADAT6
ADAT5
ADAT4
ADAT3
ADAT2
ADAT1
ADAT0
00
ADC Data
Register
97
ACON
ADEN
ADS1
ADS0
ADST
ADSF
00
ADC Control
Register
AI06627
Input
MUX
ACH0
ACH1
ACH2
ACH3
ACON
INTERNAL BUS
ADAT
AVREF
Ladder
Resistor
D
ecode
S/H
Successive
Approximation
Circuit
Conversion
Complete
Interrupt
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