參數(shù)資料
型號： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 86/164頁
文件大小： 1133K
代理商： UPSD3233
μ
PSD3200 FAMILY
86/164
DRAFT(Thursday 20 June 2002, 13:15).
The USCL 8-bit Prescaler Register for USB is at
E1h. TheUSCL should be loaded with a value that
results in a clock rate of approximately 6 MHz for
the USB using the following formula:
USB clock input =
(F
OSC
/ 2) / (Prescaler register value +1)
Where Fosc is the MCU clock input frequency.
Table 78. USBSFR Memory Map
Transceiver
USB Physical Layer Characteristics.
The
lowing section describes the
μ
PSD3200 Family
compliance to the Chapter 7 Electrical section of
the USB Specification, Revision 1.1. The section
contains all signaling, and physical layer specifica-
tions necessary to describe a low speed USB
function.
Low Speed Driver Characteristics.
The
μ
PSD3200 Family device uses a differential out-
put driver to drive the Low Speed USB data signal
onto the USB cable. The output swings between
the differential high and low state are well bal-
anced to minimize signal skew. The slew rate con-
trol on the driver minimizes the radiated noise and
cross talk on the USB cable. The driver’s outputs
fol-
support three-state operation to achieve bi-direc-
tional half duplex operation. The
μ
PSD3200 Fam-
ily driver tolerates a voltage on the signal pins of -
0.5V to 3.6V with respect to local ground reference
without damage. The driver tolerates this voltage
for 10.0
μ
s while the driver is active and driving,
and tolerates this condition indefinitely when the
driver is in its high impedance state.
A low speed USB connection is made through an
unshielded, untwisted wire cable a maximum of 3
meters in length. The rise and fall time of the sig-
nals onthis cable are well controlled to reduce RFI
emissions while limiting delays, signaling skews
and distortions. The
μ
PSD3200 Family driver
reaches the specified static signal levels with
smooth rise and fall times, resulting in segments
SFR
Addr
Reg
Name
Bit Register Name
Reset
7
6
5
4
3
2
1
0
E1
USCL
00
8-bit
Prescaler for
USB logic
E6
UDT1
UDT1.7
UDT1.6
UDT1.5
UDT1.4
UDT1.3
UDT1.2
UDT1.1
UDT1.0
00
USB Endpt1
Data Xmit
E7
UDT0
UDT0.7
UDT0.6
UDT0.5
UDT0.4
UDT0.3
UDT0.2
UDT0.1
UDT0.0
00
USB Endpt0
Data Xmit
E8
UISTA
SUSPND
—
RSTF
TXD0F
RXD0F
RXD1F
EOPF
RESUMF
00
USB
Interrupt
Status
E9
UIEN
SUSPNDIE
—
—
TXD0IE
RXD0IE
TXD1IE
EOPIE RESUMIE
00
USB
Interrupt
Enable
EA UCON0
TSEQ0
STALL0
TX0E
RX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
00
USB Endpt0
Xmit Control
EB UCON1
TSEQ1
EP12SEL
—
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
00
USB Endpt1
Xmit Control
EC UCON2
—
—
—
SOUT
EP2E
EP1E
STALL2
STALL1
00
USB Control
Register
ED
USTA
RSEQ
SETUP
IN
OUT
RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0
00
USB Endpt0
Status
EE
UADR
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
00
USB
Address
Register
EF
UDR0
UDR0.7
UDR0.6
UDR0.5
UDR0.4
UDR0.3
UDR0.2
UDR0.1
UDR0.0
00
USB Endpt0
Data Recv
相關(guān)PDF資料
PDF描述
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