參數(shù)資料
型號(hào)： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁(yè)數(shù)： 22/164頁(yè)
文件大?。?/td> 1133K
代理商： UPSD3233
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μ
PSD3200 FAMILY
22/164
DRAFT(Thursday 20 June 2002, 13:15).
dressable, and each one can be treated as a
separate single-bit port. The instructions that ac-
cess these bits are not just conditional branches,
but a complete menu of move, set, clear, comple-
ment, OR and ANDinstructions. These kinds of bit
operations are not easily obtained in other archi-
tectures with any amount of byte-oriented soft-
ware.
The instruction set for the Boolean processor is
shown in Table 12. All bits accesses are by direct
addressing.
Bit addresses 00h through 7Fh are in the Lower
128, and bit ad-dresses 80h through FFh are in
SFR space.
Note how easily an internal flag can be moved to
a port pin:
MOV C,FLAG
MOV P1.0,C
In this example, FLAG is the name of any addres-
sable bit in the Lower 128 or SFR space. An I/O
line (the LSB of Port 1, in this case) is set or
cleared dependingon whether the flag bit is 1 or0.
The Carry bit in the PSW is used as the single-bit
Accumulator of the Boolean processor. Bit instruc-
tions that refer to the Carry bit as C assemble as
Carry-specific instructions (CLR C, etc.). The Car-
ry bit also has a direct address, since it resides in
the PSW register, which is bit-addressable.
Note that the Boolean instruction set includesANL
and ORL operations, but not the XRL (Exclusive
OR) operation. An XRL operation is simple to im-
plement in software. Suppose, for example,it isre-
quired to form the Exclusive OR of two bits:
C = bit 1 .XRL. bit2
The software to do that could be as follows:
MOV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)
First, bit1 is moved to the Carry. If bit2 = 0, then C
now contains the correct result.That is,bit1 .XRL.
bit2 = bit1 if bit2 = 0. On the other hand, if bit2 = 1,
C now contains the complement of the correct re-
sult. It need only be inverted (CPL C) to complete
the operation.
This codeuses theJNB instruction, one of a series
of bit-test instructions which execute a jump if the
addressed bit is set (JC, JB, JBC) or if the ad-
dressed bit is not set (JNC, JNB). In the above
case, bit2 is being tested, and if bit2 = 0, the CPL
C instruction is jumped over.
JBC executes the jump if the addressed bit is set,
and also clears the bit. Thus a flag can be tested
and cleared in one operation. All the PSW bits are
directly addressable, so the Parity bit, or the gen-
eral-purpose flags, for example, are also available
to the bit-test instructions.
Relative Offset
The destination address for these jumps is speci-
fied to the assembler by a label or by an actual ad-
dress
in
Program
memory.
destination address assembles to a relative offset
byte. This is a signed (two’s complement) offset
bytewhich isadded to the PC in two’scomplement
arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127
Program Memory bytesrelative to the first bytefol-
lowing the instruction.
How-ever,
the
Table 13. Unconditional Jump Instructions
Jump Instructions
Table 13 shows the list of unconditional jump in-
structions. The table lists a single “JMP add” in-
struction, but in fact there are three SJMP, LJMP,
and AJMP, which differ in the format of the desti-
nation address. JMPis a generic mnemonic which
can be used if the programmer does not care
which way the jump is en-coded.
The SJMP instruction encodes the destination ad-
dress as a relative offset, as described above. The
instruction is 2 bytes long, consisting of the op-
code and the relative offset byte. The jump dis-
tance is limited to a range of -128 to +127 bytes
relative to the instruction following the SJMP.
The LJMP instruction encodes the destination ad-
dress as a 16-bit constant. The instruction is 3
bytes long, consisting of the opcode and two ad-
dress bytes. The destination address can be any-
where in the 64K ProgramMemory space.
The AJMP instruction encodes the destination ad-
dress as an 11-bit constant. The instruction is 2
bytes long, consisting of the opcode, which itself
contains 3 of the 11 address bits, followed by an-
other byte containing the low 8 bits of the destina-
tion address. When the instruction is executed,
these 11 bits are simply substituted for the low 11
bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same
2K block as the instruction following the AJMP.
Mnemonic
Operation
JMP addr
Jump to addr
JMP @A+DPTR
Jump to A+DPTR
CALL addr
Call Subroutine at addr
RET
Return from subroutine
RETI
Return from interrupt
NOP
No operation
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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