參數(shù)資料
型號(hào)： uPSD3233
廠(chǎng)商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁(yè)數(shù)： 34/164頁(yè)
文件大?。?/td> 1133K
代理商： UPSD3233
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μ
PSD3200 FAMILY
34/164
DRAFT(Thursday 20 June 2002, 13:15).
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows.
I
INT0 external interrupt
I
2nd USART interrupt
I
Timer0 interrupt
I
I
2
C interrupt
I
INT1 external interrupt (or ADC interrupt)
I
DDC interrupt
I
Timer1 interrupt
I
USB interrupt
I
USART interrupt
I
Timer2 interrupt
External Int0
I
The INT0canbe eitherlevel-active ortransition-
active depending on bit IT0 in register TCON.
The flag that actually generates this interrupt is
bit IE0 in TCON.
I
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
I
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
Timer 0 and 1 Interrupts
I
Timer0 and Timer1 interrupts are generated by
TF0 and TF1 which are set by an overflow of
theirrespectiveTimer/Counterregisters(except
for Timer0 in mode3).
I
These flags are cleared by the internal
hardware when the interrupt is serviced.
Timer 2 Interrupt
I
Timer2 interrupt is generated by TF2 which is
set byan overflow of Timer2.This flaghas to be
cleared by the software - not by hardware.
I
It is also generated by the T2EX signal (timer 2
external interrupt P1.1) which is controlled by
EXEN2 and EXF2 bits in the T2CON register.
This is the definition of Timer 2 as per 90C320
definition.
I
2
C Interrupt
I
The interruptof the I
2
C is generated bybit INTR
in the register S2STA.
I
This flag is cleared by hardware.
External Int1
I
The INT1 canbe either level active ortransition
active depending on bit IT1 in register TCON.
The flag that actually generates this interrupt is
bit IE1 in TCON.
I
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
I
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
I
The ADC can take over the External INT1 to
generate an interrupt on conversion being
completed
DDC Interrupt
I
The DDC interrupt is generated either by bit
INTR in the S1STA register for DC2B protocol
or by bit DDC interrupt in the DDCCON register
for DDC1 protocol or by bit SWHINT bit in the
DDCCON register when DDC protocol is
changed from DDC1 to DDC2.
I
Flags excepttheINTRhave to becleared by the
software. INTR flag is cleared by hardware.
USB Interrupt
I
The USB interruptis generatedwhen endpoint0
has transmitted a packet or received a packet,
when endpoint1 orendpoint2 has transmitted a
packet, when the suspend or resume state is
detected and every EOP received.
I
When the USB interrupt is generated, the
corresponding request flag must be cleared by
software. The interrupt serviceroutine will have
to checkthe various USB registers todetermine
the source and clear the corresponding flag.
I
Please see thededicated interrupt control
registers for the USB peripheral for more
information.
I
The USART interrupt is generated by RI
(receive interrupt) OR TI (transmit interrupt).
USART Interrupt
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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