參數(shù)資料
型號(hào)： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 117/164頁
文件大小： 1133K
代理商： UPSD3233
117/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Table 92. I/O Port Latched Address Output Assignments
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDsoft, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE) or a product term from
the PLD AND Array. The outputs from the Input
Macrocells (IMC) drive the PLD input bus and can
be read by the MCU. See the section entitled “In-
put Macrocell”, on page 114.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft, some
by the MCU writing to the Control Registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft must be pro-
grammed into the device and cannot be changed
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
Address Input, and Peripheral I/O modes are the
only modes that must be defined before program-
ming the device. All other modes can be changed
by the MCU at run-time. See Application Note
AN1171 for more detail.
Table 90 summarizes which modes are available
on each port. Table 93 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O mode, theMCU uses the I/O Ports
block toexpand itsown I/O ports.By setting up the
CSIOP space, the ports on the PSD Module are
mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 82.
A port pin can be putinto MCU I/O modeby writing
a 0 to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled “Peripheral I/O Mode”, on
page 117. When the pin is configured as an out-
put, the contentof the Data Out Registerdrives the
pin. When configured as an input, the MCU can
read the port input through the Data In buffer. See
Figure 60.
Ports C and D do not have Control Registers, and
are in MCU I/O modeby default. Theycan be used
for PLD I/O if equations are written for them inPS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from thePLD, or by resetting the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is defined for a PLD
input signal in PSDsoft. The PLD I/O mode is
specified in PSDsoft by declaring the port pins,
and then writing an equation assigning the PLD I/
O to a port.
Address Out Mode
Address Out Mode can be used to drive latched
MCU addresses on to the port pins. These port
pins can, in turn, drive external devices. Either the
output enable orthe corresponding bits of both the
Direction Register and Control Register must be
set to a 1 for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
92 for the address output pin assignments on
Ports A and B for various MCUs.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a 1. Figure 61
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equationfor PSEL0 and/or PSEL1 must
be written in PSDsoft. The buffer is tri-stated when
PSEL0 or PSEL1 is not active.
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Port B (PB7-PB4)
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
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