參數資料
型號： uPSD3233
廠商： 意法半導體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統器)
中文描述： 閃存可編程系統器件與8032微控制器內核（嵌入高速“8032微控制器核”的閃存型可編程系統器）
文件頁數： 45/164頁
文件大?。?/td> 1133K
代理商： UPSD3233
45/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
SUPERVISORY
There are four ways to invoke a reset and initialize
the
μ
PSD3200 Family.
I
Via the external RESET pin
I
Via the internal LVR Block.
I
Via USB bus reset signaling.
I
Via Watch Dog timer
The reset mechanism is illustrated in Figure 19.
Figure 19. Reset Configuration
Each reset source will cause an internal reset sig-
nal active. The CPU responds by executing an in-
ternal reset and puts the internal registers in a
defined state. This internal reset is also routed as
an active low reset input to the PSD Module.
External Reset
The reset pin RESET is connected to a Schmitt
trigger for noise reduction. Areset is accomplished
by holdingthe RESET pin LOW for at least 1msat
power up while the oscillator is running. Refer to
AC spec on other reset timing requirements.
Low V
DD
Voltage Reset
An internal reset is generated by the LVR circuit
when theVDD dropsbelow theresetthreshold. Af-
ter VDD reaching back up to the reset threshold,
the reset signal will remain asserted for 10 ms be-
fore it is released. On initial power-up the LVR is
enabled (default). After power-up the LVR can be
disabled via the LVREN bit in the PCON Register.
Note that the LVRlogic is still functional inboth the
Idle and Power down modes.
The reset threshold:
I
5V operation:
4V +/- 0.25V
I
3.3V operation: 2.5V +/-0.2V
This logic supports approximately 0.1V of hystere-
sis and 1
μ
s noise-cancelling delay.
Watchdog Timer Overflow
The Watchdog timer generates an internal reset
when its 22-bit counter overflows. See Watchdog
Timer section for details.
USB Reset
The USB reset is generated by a detection on the
USB bus reset signal. A single-end zero on its up-
stream portfor 4 to 8 times will setRSTF bit inUIS-
TA register. The detection will also generate the
RESET signal to reset the CPU and other periph-
erals in the MCU.
AI06621
Reset
CPU
&
PERI.
Noise
Cancel
LVR
S
Q
R
CPU
Clock
Sync
10ms
Timer
USB Reset
WDT
PSD_RST
“
Active Low
10ms at 40Mhz
50ms at
8Mhz
相關PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內核和16Kbit SRAM的FLASH可編程系統器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內核的FLASH可編程系統器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內核的FLASH可編程系統器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關代理商/技術參數
參數描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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