參數(shù)資料
型號(hào): uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 69/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
69/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Serial Status Register (SxSTA: S1STA, S2STA)
SxSTA is a read-only register. The contents of this
register may be used as a vector to a service rou-
tine. This optimized the response time of the soft-
ware and consequently that of the I
2
C-bus. The
status codes for all possible modes of the I
2
C-bus
interface are given Table 52.
Table 51. Serial Status Register (SxSTA)
Table 52. Description of the SxSTA Bits
Note: 1. Interrupt flag bit (INTR, SxSTA bit 5) is cleared by Hardware as reading SxSTA register.
2. I
C interrupt flag (INTR) can occur in below case. (except DDC2B mode at SWENB=0)
This flag is set, and an interrupt is generated, after
any of the following events occur.
1. Own slave address has been received during
AA = 1: ack_int
2. The general call address has been received
while GC(SxADR.0) = 1 and AA = 1:
3. A data byte has been received ortransmitted in
master mode (even if arbitration is lost): ack_int
4. A data byte has been received or transmitted as
selected slave: ack_int
5. A stop condition is received as selected slave
receiver or transmitter: stop_int
Data Shift Register (SxDAT: S1DAT, S2DAT)
SxDAT contains the serial data to be transmitted
or data which has just been received. The MSB
(bit7) is transmitted or received first; that is, data
shifted from right to left.
Table 53. Data Shift Register (SxDAT: S1DAT, S2DAT)
7
6
5
4
3
2
1
0
GC
STOP
INTR
TX_MODE
BBUSY
BLOST
/ACK_REP
SLV
Bit
Symbol
Function
7
GC
General Call flag
6
STOP
Stop flag. This bit is set when a STOP condition is received
5
INTR
Interrupt flag. This bit is set when an I C Interrupt condition is requested
4
TX_MODE
Transmission mode flag.
This bit is set when the I C is a transmitter; otherwise this bit is reset
3
BBUSY
Bus Busy flag.
This bit is set when the bus is being used by another master; otherwise, this bit is reset
2
BLOST
Bus Lost flag.
This bit is set when the master loses the bus contention; otherwise this bit is reset
1
/ACK_REP
Acknowledge Responseflag.
This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal
0
SLV
Slave mode flag.
This bit is set when the I C plays role in the slave mode; otherwise this bit is reset
7
6
5
4
3
2
1
0
SxDAT7
SxDAT6
SxDAT5
SxDAT4
SxDAT3
SxDAT2
SxDAT1
SxDAT0
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