參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 63/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
63/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Table 46. Description of the ACON Bits
The ASCL should be loaded with a value that re-
sults ina clock rate of approximately 6 MHz for the
ADC using the following formula:
ADC clock input = (Fosc / 2) / (Prescaler register
value +1)
Where Fosc is the MCU clock input frequency
The conversion time for the ADC can be calculat-
ed as follows:
ADC Conversion Time = 8 clock * 8bits * (ADC
Clock) ~= 10.67usec (at 6 MHz)
ADC Interrupt
TheADSF bit inthe ACON registeris setto 1 when
the A/D conversion is complete. The status bit can
be driven by the MCU, or it can be configured to
generate a falling edge interrupt when the conver-
sion is complete.
The ADSF interrupt is enabled by setting the ADS-
FINT bit in the PCON register. Once the bit is set,
the external INT1 interrupt is disabled and the
ADSF interrupt takes over as INT1. INT1 must be
configured as if it is an edge interrupt input. The
INP1 pin (p3.3) is available for general I/O func-
tions, or Timer1 gate control.
Bit
Symbol
Function
7 to 6
Reserved
5
ADEN
ADC enable bit:
0 : ADC shut off and consumes no operating current
1 : enable ADC
4
Reserved
3 to 2
ADS1, ADS0
Analog channel select
0, 0
Channel0 (ACH0)
0, 1
Channel1 (ACH1)
1, 0
Channel2 (ACH2)
1, 1
Channel3 (ACH3)
1
ADST
ADC start bit:
0: force to zero
1 : start an ADC; after one cycle, bit is cleared to “0”
0
ADSF
ADC status bit:
0 : A/D conversion is in process
1 : A/D conversion is completed, not in process
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