參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 40/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
μ
PSD3200 FAMILY
40/164
DRAFT(Thursday 20 June 2002, 13:15).
Power Control Register
The modes Idle and Power-down are activated by
software via the PCON register.
Table 26. Power Control Register (PCON)
Table 27. Description of the PCON Bits
Note: 1. See the T2CON register for details of the flag description
Idle Mode
The instruction that sets PCON.0 is the last in-
struction executed in the normal operating mode
before idle mode is activated. Once in the idle
mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM and All other registers
maintain their data during idle mode.
There are three ways to terminate the idle mode.
I
Activation of any enabled interrupt will cause
PCON.0 to be cleared byhardware terminating
Idle mode. The interrupt is serviced, and
following return from interrupt instruction RETI,
the next instruction to be executed will be the
one which follows the instruction that wrote a
logic 1 to PCON.0.
I
External hardware reset: the hardware reset is
required to be active for two machine cycle to
complete the reset operation.
I
Internal reset: the microcontroller restarts after
3 machine cycles in all cases.
Power-Down Mode
The instruction that sets PCON.1 is the last exe-
cuted prior to going into the Power-down mode.
Once in Power-down mode, the oscillator is
stopped. The contents of theon-chip RAM and the
Special Function Register are preserved.
The power-down mode can be terminated by an
external RESET.
SFR
Addr
Reg
Name
Bit Register Name
ValueComments
7
6
5
4
3
2
1
0
87
PCON
SMOD
SMOD1
LVREN ADSFINT RCLK1
TCLK1
PD
IDLE
00
Power Ctrl
Bit
Symbol
Function
7
SMOD
Double baud data rate bit UART
6
SMOD1
Double baud data rate bit 2nd UART
5
LVREN
LVR disable bit (active High)
4
ADSFINT
Enable ADC interrupt
3
RCLK1
1
Received clock flag (UART 2)
2
TCLK1
1
Transmit clock flag (UART 2)
1
PD
Activate Power-down mode (High enable)
0
IDL
Activate Idle mode (High enable)
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