參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 143/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
143/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Table 114. External Data Memory AC Characteristics (with the 5V MCU Module)
Note: 1. Conditions (in addition to those in Table 108, V
CC
= 4.5 to 5.5 V): V
SS
= 0 V; C
L
forPort 0, ALE and PSEN output is 100 pF; C
L
for
other outputs is 80 pF
Table 115. External Clock Drive (with the 5V MCU Module)
Note: 1. Conditions (in addition to those in Table 108, V
CC
= 4.5 to 5.5 V): V
SS
= 0 V; C
L
forPort 0, ALE and PSEN output is 100 pF; C
L
for
other outputs is 80 pF
Symbol
Parameter
1
40 MHz Oscillator
Variable Oscillator
1/t
CLCL
= 24 to 40 MHz
Unit
Min
Max
Min
Max
t
RLRH
RD pulse width
120
6t
CLCL
– 30
ns
t
WLWH
WR pulse width
120
6t
CLCL
– 30
ns
t
LLAX2
Address hold after ALE
10
t
CLCL
– 15
ns
t
RHDX
RD to valid data in
75
5t
CLCL
– 50
ns
t
RHDX
Data hold after RD
0
0
ns
t
RHDZ
Data float after RD
38
2t
CLCL
– 12
ns
t
LLDV
ALE to valid data in
150
8t
CLCL
– 50
ns
t
AVDV
Address to valid data in
150
9t
CLCL
– 75
ns
t
LLWL
ALE to WR or RD
60
90
3t
CLCL
– 15
t
CLCL
+ 15
ns
t
AVWL
Address valid to WR or RD
70
4t
CLCL
– 30
ns
t
WHLH
WR or RD High to ALE High
10
40
t
CLCL
– 15
t
CLCL
+ 15
ns
t
QVWX
Data valid to WR transition
5
t
CLCL
– 20
ns
t
QVWH
Data set-up before WR
125
7t
CLCL
– 50
ns
t
WHQX
Data hold after WR
5
t
CLCL
– 20
ns
t
RLAZ
Address float after RD
0
0
ns
Symbol
Parameter
1
40 MHz Oscillator
Variable Oscillator
1/t
CLCL
= 24 to 40 MHz
Unit
Min
Max
Min
Max
t
RLRH
Oscillator period
25
41.7
ns
t
WLWH
High time
10
t
CLCL
– t
CLCX
ns
t
LLAX2
Low time
10
t
CLCL
– t
CLCX
ns
t
RHDX
Rise time
10
ns
t
RHDX
Fall time
10
ns
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uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
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