參數(shù)資料
型號： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 56/164頁
文件大?。?/td> 1133K
代理商： UPSD3233
μ
PSD3200 FAMILY
56/164
DRAFT(Thursday 20 June 2002, 13:15).
Mode 1,3 Baud Rate = fosc / (32 x [65536 -
(RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of
RC2H and RC2L taken as a 16-bit unsigned inte-
ger.
Timer 2 also be used as the baud rate generating
mode. This mode is valid only if RCLK + TCLK = 1
in T2CON or inPCON. Note that a roll-over in TH2
does not set TF2, and will not generate an inter-
rupt. Therefore, the Timer interrupt does not have
to be disabled when Timer 2 is in the baud rate
generator mode. Note too, that if EXEN2 is set, a
1-to-0 transition in T2EX will set EXF2 but will not
cause areload from(RCAP2H, RCAP2L) to (TH2,
TL2). Thus when Timer 2 is in use as a baud rate
generator, T2EX can be used as an extraexternal
interrupt, if desired.
It should be noted that when Timer 2 is running
(TR2 = 1) in “timer” function in the baud rate gen-
erator mode, one should not try to read or write
TH2 or TL2. Under these conditions the timer is
being incremented every state time, and the re-
sults of a read or write may not be accurate. The
RC registers may be read, but should not be writ-
ten to, because a write might overlap a reload and
cause write and/or reload errors. Turn the timer off
(clear TR2) before accessing the Timer 2 or RC
registers, in this case.
More About Mode 0.
Serial data enters and exits
through RxD.TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed a 1/6 the CPU clock frequency.
Figure 26 shows a simplified functional diagram of
the serial port in Mode 0, and associated timing.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “write to
SBUF” signal at S6P2 also loads a 1 into the 9th
position of the transmit shift register and tells the
TX Control block to commence a transmission.
The internal timing is such that one full machine
cycle will elapse between “write to SBUF” and ac-
tivation of SEND.
SEND enables the outputof theshift registerto the
alternate out-put function line of RxD and also en-
able SHIFT CLOCK to the alternate output func-
tion line of TxD. SHIFT CLOCK is low during S3,
S4, and S5 of every machine cycle, and high dur-
ing S6, S1, and S2. At S6P2 of every machine cy-
cle in which SEND is active, the contents of the
transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in
from the left. When the MSB of the data byte is at
the output position of the shift register, then the 1
that was initially loaded into the 9th position, is just
to the left of the MSB, and all positions to the left
of that contain zeros. This condition flags the TX
Control block to do one last shift and then deacti-
vateSEND andset T1. Both of these actionsoccur
at S1P1. Both of these actions occur at S1P1 of
the 10th machine cycle after “write to SBUF.”
Reception is initiated by the condition REN= 1 and
R1 = 0. At S6P2 ofthe next machine cycle, the RX
Control unitwrites thebits 11111110 to thereceive
shift register, and in the next clock phaseactivates
RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate
output function line of TxD. SHIFT CLOCK makes
transitions at S3P1 and S6P1 of every machine
cycle in which RECEIVE is active, the contents of
the receive shift register are shifted to the left one
position. The value that comes in from the right is
the value that wassampled at the RxD pinat S5P2
of the same machine cycle.
As data bits come in from the right, 1s shift out to
the left. When the 0 that was initially loaded into
the right-most position arrives at the left-most po-
sition in the shift register, it flags the RX Control
block to do one last shift and load SBUF. At S1P1
of the 10th machine cycle after the write to SCON
that cleared RI, RECEIVE is cleared as RI is set.
More About Mode 1.
Ten bits are transmitted
(through TxD), or received (through RxD): a start
bit (0),8 data bits (LSBfirst). and a stop bit (1). On
receive, the stop bitgoes into RB8 in SCON. In the
μ
PSD3200 Family the baud rate is determined by
the Timer 1 over-flow rate.
Figure 28 shows a simplified functional diagram of
the serial port in Mode 1, and associated timings
for transmit receive.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “write to
SBUF” signalalso loads a 1 into the 9thbit position
of the transmit shift register and flags the TX Con-
trol unit that a transmission is requested. Trans-
mission actually commences at S1P1 of the
machine cycle following the next rollover in the di-
vide-by-16 counter. (Thus, the bit times are syn-
chronized to the divide-by-16 counter, not to the
“write to SBUF” signal.)
The transmission begins with activation of SEND
which puts the start bit at TxD. One bit time later,
DATA is activated, which enables the output bit of
the transmit shift register to TxD. The first shift
pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked
in from the left. When the MSB of the data byte is
at the output position of the shift register, then the
1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the
left of that contain zeros. This condition flags the
TX Control unit to do one last shift and then deac-
tivate SEND and set TI. This occurs at the 10th di-
vide-by-16 rollover after “write to SBUF.”
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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