參數(shù)資料
型號(hào): PM5372-BI
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 92/169頁
文件大小: 989K
代理商: PM5372-BI
TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
92
Register 0047H: SSWT TJ0FP Delay
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
R/W
TJ0DLY[13]
0
Bit 12
R/W
TJ0DLY[12]
0
Bit 11
R/W
TJ0DLY[11]
0
Bit 10
R/W
TJ0DLY[10]
0
Bit 9
R/W
TJ0DLY[9]
0
Bit 8
R/W
TJ0DLY[8]
0
Bit 7
R/W
TJ0DLY[7]
0
Bit 6
R/W
TJ0DLY[6]
0
Bit 5
R/W
TJ0DLY[5]
1
Bit 4
R/W
TJ0DLY[4]
0
Bit 3
R/W
TJ0DLY[3]
0
Bit 2
R/W
TJ0DLY[2]
1
Bit 1
R/W
TJ0DLY[1]
1
Bit 0
R/W
TJ0DLY[0]
0
This register controls the delay from the RJ0FP input signal to the assertion of the TJ0FP signal,
meant to signify the transmission of J0s from all transmit ports TP[64:1]/TN[64:1].
TJ0DLY[13:0]
The transmit transport frame delay bits (TJ0DLY[13:0]) controls the delay from the RJ0FP
pulse clock cycle, in SYSCLK cycles, inserted by the TSE before asserting the TJ0FP signal.
The delay between RJ0FP and the assertion of TJ0FP will be TJ0DLY + 2 cycles. It is
suggested that TJ0DLY is set so TJ0FP assertion signifies the departure of all J0s from the
transmit ports. If TJ0FP is used for that purpose, TJ0DLY should be set to RJ0DLY+ 47.
Figure 21 illustrates the relationship between RJ0FP, RJ0DLY and TJ0DLY.
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