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| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 138/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
138
A device update of all the counters can be achieved by writing to the TSE Master Clock Activity
and Accumulation Trigger register (0001H). The TIP bit in the TSE Master Clock Activity and
Accumulation Trigger register can be polled to determine when all the counter values have been
transferred and are ready to be read.
12.11 “J0” Synchronization of the TSE in a CHESS System
Any TSE/TBS fabric can be viewed as a collection of different stages. For example, a Time-
Space-Time switch could be constructed with five datapath stages:
1. Ingress load devices (e.g. SPECTRA-2488)
2. Ingress TBS devices
3. TSE devices
4. Egress TBS devices
5. Egress load devices (e.g. SPECTRA-2488)
Note that in some cases, one physical device may serve in two stages, such as stages 1 and 5 or
stages 2 and 4. STS-12 frames are pipelined through this fabric in a regular fashion, under
control of a single clock frequency (77.76 MHz). In order to maintain valid framing for the group
of STS-12 streams, the datapath devices must be coordinated with one another. The first step in
this coordination is the use of a global frame synchronization pulse to mark the position of frame
boundaries as they enter the fabric. However, since each device in the system datapath sees the
STS-12 frames at a different latency than other devices, there must be a mechanism to account for
the individual latencies at different points along the datapath.
The most significant source of delay is the cumulative latency of the devices that lie along the
system datapath. To accommodate different system arrangements, a synchronization frame pulse
and a programmable frame delay register are used to re-frame the STS-12 streams for each
system datapath device. In the TSE, this FIFO is 24-words deep and is controlled by the RJ0FP
pin along with the RJ0DLY register. This frame delay register is used to inform the TSE of the
latency between a frame pulse on the RJ0FP pin and the presence of J0 characters in the FIFOs so
that a re-framing mechanism can be triggered at the appropriate time. Because the J0 characters
may lie at different FIFO depths, due to skew between links, this re-framing can be achieved by
realigning the FIFO read pointers to match the J0 positions.
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