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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
8
9.1.6
Clock Synthesis Unit (CSU) ...................................................................48
Receive 8B/10B Frame Aligner (R8FA)............................................................48
9.2.1
Character Alignment...............................................................................49
9.2.2
Frame Alignment ....................................................................................50
9.2.3
FIFO Buffer.............................................................................................51
9.2.4
Frame Counter .......................................................................................51
Ingress Time Switch Element (ITSE)................................................................51
Space Switch Stage (SSWT)............................................................................51
Egress Time Switch Element (ETSE)...............................................................52
Transmit 8B/10B Disparity Encoder (T8DE).....................................................52
Clock Synthesis and Transmit Reference Digital Wrapper (CSTR) .................53
Fabric Latency..................................................................................................53
JTAG Support ...................................................................................................53
9.10
Microprocessor Interface..................................................................................54
10
Normal Mode Register Description...........................................................................59
11
Test Features Description .......................................................................................121
11.1
JTAG Test Port................................................................................................122
11.1.1
Boundary Scan Cells............................................................................123
12
Operation.................................................................................................................126
12.1
Power Conservation .......................................................................................126
12.2
LVDS Optimizations........................................................................................127
12.3
LVDS Hot Swapping.......................................................................................128
12.4
LVDS Trace Lengths.......................................................................................128
12.5
JTAG Support .................................................................................................129
12.5.1
TAP Controller ......................................................................................131
12.5.2
States....................................................................................................133
12.5.3
Instructions ...........................................................................................134
12.6
Initialization Procedure ...................................................................................135
12.7
Interrupt Service Routine................................................................................136
12.8
Interpreting the Status of Receive Decoders..................................................136
12.9
Accessing Indirect Registers..........................................................................137
12.10
Using the Performance Monitoring Features..................................................137
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9