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參數(shù)資料
| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 52/169頁(yè) |
| 文件大小： | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
52
The SSWT is equivalent to a crossbar, with separate switch settings taken from control tables for
each egress channel for each 8B/10B time period (77.76 MHz). Multicast is supported by
permitting any number of output columns to take a sample from any input row at the same time.
The SSWT contains two sets or pages of control registers to control the switching function. Each
set of control registers consists of twelve registers (one per time step) of six bits (to select among
64 sources) for each of 64 egress ports. These registers are accessible from the microprocessor
interface; they constitute 2*12*6*64 = 9216 bits. Selection of the switching page is determined
by the device CMP pin, or through the microprocessor control interface.
Another control register in the SSWT allows specification of the delay between the system
synchronization pulse and J0 arrivals at the TSE receive analog blocks.
The SSWT is implemented by a set of input-selector muxes at each output.
9.5
Egress Time Switch Element (ETSE)
The ETSE accepts STS-12-aligned cyclic groups of twelve STS-1 samples over twelve time steps
from the Space Switch, and outputs these samples in an arbitrary Time permutation to the Egress
Ports. The time permutation is determined by the contents of two switching control register sets
or pages, each of which describes which STS-1 sample should be output during the ith (1 <= i
<=12) STS-1 time slot. These control registers are accessible via the microprocessor bus.
Selection of the switching page is determined by the device CMP pin, and on a per ETSE basis
through the microprocessor control interface.
The ETSE can also be set in a BYPASS mode in which no switching is done. When in BYPASS
mode, the latency of the ETSE is the same as when it is in DYNAMIC (switching) mode.
The egress time stage is implemented as two 12 STS-1 buffers, one to accumulate the incoming
stream and the other to accept twelve STS-1s in parallel and then deliver these samples in the
order specified by the switching control settings.
9.6
Transmit 8B/10B Disparity Encoder (T8DE)
The T8DE block corrects the running disparity of an 8B/10B character stream and buffers data in
a FIFO before transmission to the PISO block. A total of 64 T8DE blocks are instantiated in the
TSE device.
The input data to the T8DE blocks originated from the R8FA blocks at which point they have
correct running disparity. However, due to the time and space re-arrangement activities of the
TSE, the running disparity is no longer consistent. The T8DE block inverts the 6B and 4B sub-
characters to ensure correct running disparity.
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