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參數(shù)資料
| 型號(hào)： | PM5372-BI |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 51/169頁(yè) |
| 文件大?。?/td> | 989K |
| 代理商： | PM5372-BI |
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TSE Transmission Switch Element Datasheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1991258, Issue 7
51
The out of position J0 counter is incremented for each K28.5 character it encounters that is out of
position with respect to the current frame alignment. The counter saturates at 3. When the block is
frame aligned, the counter is cleared by an in position K28.5 character. When the block is not
aligned, the counter is cleared by the next occurrence of next 2 K28.5 characters appearing
separated by 125.0 us.
9.2.3
FIFO Buffer
The FIFO buffer sub-block provides isolation between the timing domain of the associated
receive LVDS link and that of the system clock (SYSCLK). Aligned 8B/10B characters are
written into a 10-bit by 24-word deep FIFO at the line clock rate. Data is read from the FIFO at
every SYSCLK cycle.
9.2.4
Frame Counter
The Frame Counter sub-block keeps track of the octet identity of the outgoing data stream. It is
initialized by a delayed version of the RJ0FP signal. It adjusts the read pointer so the J0 byte
location in the FIFO is sampled at specific device wide event. All R8Fas are then aligned to
transmit their J0 byte at this event.
9.3
Ingress Time Switch Element (ITSE)
The ITSE accepts STS-12-aligned cyclic groups of twelve STS-1 samples over twelve time steps
from the R8Fas, and distributes these samples in an arbitrary Time permutation to the Space
Switch Stage. The time permutation is determined by the contents of two switching control
register sets or pages, each of which describes which STS-1 sample should be output during the
i
th
(1 <= i <=12) STS-1 time slot. These control registers are accessible via the microprocessor
bus. Selection of the switching page is determined by the device CMP pin, and on a per ITSE
basis through the microprocessor control interface.
The ITSE can also be set in a BYPASS mode in which no switching is done. When in BYPASS
mode, the latency of the ITSE is the same as when it is in DYNAMIC (switching) mode.
The ITSE is implemented as 2x12 STS-1 buffers, one to accumulate the incoming stream and the
other to accept twelve STS-1s in parallel and then deliver these samples in the order specified by
the switching control registers.
9.4
Space Switch Stage (SSWT)
The SSWT accepts fully aligned STS-12 streams from Ingress Time Stages at 77.76 MHz. The
space stage implements a space switch for each of the twelve times in the cyclic STS-12 time
structure, and delivers the STS-1 samples to the intended Egress LVDS Stages.
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